Compliant hermetic package

• US 20020179921A1
• Filed: 06/03/2002
• Published: 12/05/2002
• Est. Priority Date: 06/02/2001
• Status: Abandoned Application

• Current Assignee: Michael B. Cohn
• Original Assignee: Michael B. Cohn
• Inventors: Cohn, Michael B.
• Application Number:
  US10/162,515
• Publication Number:
  US 20020179921A1
• Time in Patent Office: Days
• US Class Current: 257/99
• CPC Class Codes: B81B 7/0051 between the package lid and the substrate
• CPC Class Codes: B81C 2203/019 characterised by the material or arrangement of seals between parts
• CPC Class Codes: H01L 21/50 Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/13144 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/1319 with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/81801 Soldering or alloying
• CPC Class Codes: H01L 2225/06582 Housing for the assembly, e.g. chip scale package [CSP]
• CPC Class Codes: H01L 23/10 characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
• CPC Class Codes: H01L 24/81 using a bump connector
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01019 Potassium [K]
• CPC Class Codes: H01L 2924/01023 Vanadium [V]
• CPC Class Codes: H01L 2924/01024 Chromium [Cr]
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/01049 Indium [In]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/163 : Connection portion, e.g. seal
• CPC Class Codes: H01L 2924/16315 : Shape
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 33/52 : Encapsulations

Abstract

The present invention provides a compliant seal, particularly for bonding substrates having different thermal expansion coefficients. This invention is also applicable for attaching substrates requiring a significant gap between said substrates.

Claims

1. A device with at least two substrates, wherein at least two substrates are mechanically attached to at least one compliant structure.

2. A device as in claim 1, wherein at least one of said at least two substrates is selected from the following list:

silicon wafer with at least one MEMS device, silicon substrate with at least one MEMS device, silicon wafer with at least one semiconductor device, silicon substrate with at least one semiconductor device, III-V semiconductor wafer with at least one optoelectronic device, III-V semiconductor substrate with at least one optoelectronic device, III-V semiconductor substrate with at least one semiconductor device, III-V semiconductor substrate with at least one MEMS device, low parasitic substrate, or low loss substrate.

3. A device as in claim 1 wherein said at least one compliant structure seals together at least one location between said at least two substrates.

4. A device as in claim 1 wherein at least one portion of at least one of said at least two substrates is removed after sealing.

5. A device as in claim 3 wherein said at least one compliant structure provides a seal of the type selected from the follow list:

hermetic seal, vacuum seal, or gross-leak seal.

6. A device as in claim 1 wherein said at least two substrates are electrically interconnected together.

7. A device as in claim 6 wherein said at least two substrates are electrically interconnected with compliant structures.

8. A device with at least two substrates, wherein at least two substrates are mechanically attached to at least one compliant structure, wherein said at least two substrates are bonded to each other with a bonding technique selected from the following list:

a. gold bump bonding,

b. gold bump bonding at room temperature

c. gold bump bonding near room temperature

d. bonding at room temperature

e. bonding near room temperature

f. solder bump bonding,

g. indium bump bonding,

h. polymer bump bonding,

i. bonding with gold on at least one bonding surface,

j. bonding with solder on at least one bonding surface,

k. bonding with indium on at least one bonding surface,

l. bonding with conductive polymer on at least one bonding surface,

m. bonding wherein at least one adhesive provides at least the majority of the bonding strength between said substrates,

n. bonding wherein at least one adhesive provides at least majority of the bonding strength between said substrates, and device herneticity is improved from structures which assist in sealing including but not limited of structures which comprises at least one less-gas-permeable material from deposited layers, substrate, or combination including but not limited to silicon oxide, single crystal silicon, polysilicon, silicon nitride, gold, nickel, indium, titanium, tungsten, titanium nitride, solder, other ceramics, other metals, or any combination,

o. bonding wherein at least one adhesive provides at least the majority of the bonding strength between said substrates, and device hermeticity is improved from at least one knife-blade type seal, crush-gasket type seal or a combination which comprises at least one less-gas-permeable material from deposited layers, substrate, or combination including but not limited to silicon oxide, single crystal silicon, polysilicon, silicon nitride, gold, nickel, indium, titanium, tungsten, titanium nitride, solder, other ceramics, other metals, or any combination,

p. bonding wherein at least one adhesive provides at least the majority of the bonding strength between said substrates, and device hermeticity is improved by adding at least one less gas permeable material into the adhesive or add at least one less-gas-permeable material adjacent to the adhesive by depositing layers on one or more substrates, removing materials from one or more substrates, or any combination,

q. bonding wherein a solder bond provides the majority of the bonding strength between said substrates,

r. bonding wherein a gold thermal compression bond provides the majority of the bonding strength between said substrates,

s. bonding wherein a gold compression bond provides the majority of the bonding strength between said substrates,

t. bonding wherein the majority of the bonding strength between said substrates is provided from a bonding process involving the formation of at least one amalgam,

u. bonding wherein the majority of the bonding strength between said substrates is provided from a cold welding process,

w. any combination including at least one of the above bonding processes.

9. A device as in claim 8 wherein said at least two substrates are bonded to form at least two of said device.

10. A device as in claim 9 wherein said at least two substrates are wafers of approximately the same size.

11. A device as in claim 8 wherein at least one portion of at least one of said at least two substrates is removed after bonding.

12. A device as in claim 8 wherein said bonding process seals said at least two substrates together by at least one compliant seal ring.

13. A device as in claim 8 wherein said bonding process provides a seal of the type selected from the follow list:

hermetic seal, vacuum seal, or gross-leak seal.

14. A device as in claim 8 wherein said bonding process also provides at least one electrical interconnect between said at least two substrates.

15. A device as in claim 14 wherein said at least one of said at least one electrical interconnect is a compliant electrical interconnect structure.

16. A device as in claim 15 wherein said at least one compliant seal ring is fabricated using at least one of the device layers of said at least one electrical interconnect structure.

17. A device as in claim 15 wherein said at least one complaint seal ring is fabricated using substantially the same device layers of said at least electrical interconnect structure.

19. A method as in claim 18 wherein said at least one compliant structure seals at least one location between at least two substrates with a seal of the type selected from the following list:

hermetic seal, vacuum seal, or gross-leak seal.

20. A method as in claim 19 wherein at least two substrates are electrically interconnected with a least one electrical interconnect structure.

21. A method as in claim 20 wherein said at least one compliant structure which seals at least one location between said at least two substrates and said at least one electrical interconnect structure share at least one device layer.

22. A method as in claim 21 wherein said at least two substrates are wafers of approximately the same size.

23. A method as in claim 20 wherein at least one portion of at least one of said at least two substrates is removed after sealing.

18. A method of assembly of at least two substrates with at least one compliant structure, wherein said at least one compliant structure seals at least one location between at least two substrates.