SONOS flash cells for embedded memory logic, free of drain turn-on and over-erase

• US 20020179958A1
• Filed: 09/19/2001
• Published: 12/05/2002
• Est. Priority Date: 06/02/2001
• Status: Abandoned Application

• Current Assignee: Dae Mann Kim
• Original Assignee: Dae Mann Kim
• Inventors: Kim, Dae Mann
• Application Number:
  US09/955,285
• Publication Number:
  US 20020179958A1
• Time in Patent Office: Days
• US Class Current: 257/314
• CPC Class Codes: H01L 29/40117 the electrodes comprising a charge-trapping insulator
• CPC Class Codes: H01L 29/792 with charge trapping gate insulator, e.g. MNOS-memory transistors

Abstract

A non-volatile memory apparatus and method of manufacturing the same is disclosed, which uses a silicon-oxide-nitride-oxide-silicon (SONOS) memory cell. The SONOS cell comprises the silicon substrate (S), the dielectric layers of stacked oxide-nitride-oxide (ONO), the gate electrode (S) and the source and drain terminals separated by the gate length. The programming of the cell is done by the injection of channel hot electrons into trap sites in between the oxide and the nitride layer, while erasing is done by discharging those trapped electrons via F-N tunneling. This B/L contacted SONOS cell combines both the inherent advantages of memory operation, free of drain turn-on and over-erase and the ability to harness without modification the existing flash EEPROM technology for mass production. Additionally, this B/L contacted SONOS memory apparatus has practically an identical vertical structure to that of the standard MOSFET, which makes it possible to manufacture high density as well as embedded memory chips with the use of a simpler process.

Claims

1. A nonvolatile SONOS NOR flash cell, comprising

a semiconductor substrate of a first conductivity type;

a first silicon dioxide layer formed on the semiconductor substrate;

a silicon nitride layer formed on the first silicon dioxide;

a second silicon dioxide layer formed on the silicon nitride layer;

a gate electrode formed on the second silicon dioxide layer;

source and drain junctions of a second conductivity type displaced by the gate electrode; and

a bit line contact hole formed on the drain junction.

2. The nonvolatile SONOS NOR flash cell of claim 1, wherein programming of the cell is carried out by injecting charge into the trap sites of the interface between silicon dioxide and silicon nitride layers.

3. The SONOS NOR flash cell of claim 1, wherein erasing of the cell is carried out by ejecting charge from the trap sites of the interface between the silicon dioxide and silicon nitride layers.

5. The SONOS NOR flash cell of claim 1, wherein programming of the cell is carried out by injecting charge into the trap site between the silicon dioxide and silicon nitride layers.

6. The SONOS NOR flash cell of claim 1, wherein erasing of the cell is carried out by ejecting charge from the trap site between the silicon dioxide and silicon nitride layer.

4. A NOR type nonvolatile semiconductor memory device, wherein a plurality of SONOS cells are arranged in rows and columns, drain junctions of determined SONOS cells share a bit line with each other, and source junctions of the SONOS cells are connected to ground in common, the SONOS cells comprising:

a semiconductor substrate of first conductivity type;

a first silicon dioxide layer formed on the semiconductor substrate;

a silicon nitride layer on the first silicon dioxide layer;

a second silicon dioxide layer formed on the silicon nitride layer;

a gate electrode on the second silicon dioxide layer;

source and drain junctions of a second conductivity type displaced by the gate electrode; and

a bit line contact hole formed on the drain junction.

7. A method for forming a nonvolatile semiconductor memory device containing SONOS cells, comprising the steps of:

(a) performing a device isolation process on a semiconductor substrate;

(b) forming a first silicon dioxide layer, a silicon nitride layer, and a second silicon dioxide layer on the semiconductor substrate;

(c) covering the first silicon dioxide layer, the silicon nitride layer, the second silicon dioxide layer on a memory cell while removing the first silicon dioxide layer, the silicon nitride and the second silicon dioxide in a peripheral area;

(d) forming a third silicon dioxide layer after step (c);

(e) forming a gate electrode on the third silicon dioxide layer by deposition and patterning of poly-silicon and tungsten silicide;

(f) forming source and drain junctions using the gate electrode as a mask;

(g) forming a bit line contact hole with the use of a photo/etching process after forming an interlayer dielectric layer followed by step (e); and

(h) forming a bit line by patterning the metal after filling the contact hole.

8. The method of claim 7, wherein in step f) the concentration of the junction of the source and drain is adjusted by repetition of a photolithographic process on the source and drain.