SEMICONDUCTOR WAFER DESIGNED TO AVOID PROBED MARKS WHILE TESTING

• US 20020180026A1
• Filed: 06/05/2001
• Published: 12/05/2002
• Est. Priority Date: 06/05/2001
• Status: Active Grant

• Current Assignee: Mind Fusion, LLC (Ascend Innovation Management, LLC)
• Original Assignee: Chipmos Technologies Incorporated (Chipmos)
• Inventors: Liu, An-Hong, Tseng, Yuan-Ping
• Granted Patent: US 6,534,853 B2
• Time in Patent Office: Days
• US Class Current: 257/692
• CPC Class Codes: G01R 31/2884 using dedicated test connectors, test elements or test circuits on the IC under test G01R31/2855 takes precedence
• CPC Class Codes: H01L 22/34 Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line switching, multiplexing, gating devices G01R19/25; process control with lithography, e.g. dose control, G03F7/20; structures for alignment control by optical means G03F7/70633
• CPC Class Codes: H01L 2224/02166 Collar structures
• CPC Class Codes: H01L 2224/02377 Fan-in arrangement

Abstract

A semiconductor wafer is disclosed for avoiding probed marks while testing. The wafer has a plurality of metal interconnects, each metal interconnect connecting underlying bonding pad, corresponding contact pad and test pad. Each contact pad being outer electrical connection terminal is connected in series by a metal interconnect between test pad and bonding pad, so that the section of the metal interconnect between bonding pad and contact pad enable be tested during probing the test pad. Furthermore, there is no probing mark on the contact pad.

Claims

1. A semiconductor wafer comprises:

a plurality of semiconductor chips, each chip having an integrated circuit forming surface formed on the same plane of the semiconductor wafer, wherein the chip has a plurality of bonding pads on the integrated circuit forming surface;

a plurality of cutting paths, each cutting path being formed between two adjoining chips;

a plurality of metal interconnects being on the integrated circuit forming surface of the chip and electrically connecting with the corresponding bonding pad respectively;

a passivation layer covering the plurality of the metal interconnects and having a plurality of the first openings and the second openings;

a plurality of test pads located at the first openings of the passivation layer and connecting to the corresponding bonding pad through a corresponding metal interconnect; and

a plurality of contact pads being located at the second opening of the passivation layer, wherein the contact pad is connected in series with corresponding metal interconnect between the corresponding bonding pad and test pad.

2. The semiconductor wafer of claim 1, further comprising a plurality of flip chip bumps being formed on the contact pads.

3. The semiconductor wafer of claim 1, further comprising a plurality of test bumps being formed on the test pads.

4. The semiconductor wafer of claim 1, wherein the test pads locate on the cutting paths.

5. The semiconductor wafer of claim 1, wherein the test pads partially overlay on the cutting path.

6. The semiconductor wafer of claim 1, wherein the integrated circuit forming surface of the chip is rectangle and the test pads are arranged in zigzag pattern.

7. The semiconductor wafer of claim 1, wherein the integrated circuit forming surface of the chip is rectangle and the test pads are located on the two corresponding sides of the integrated circuit forming surface.

8. The semiconductor wafer of claim 1, wherein the integrated circuit forming surface of the chip is rectangle and the test pads are located around the perimeter of the integrated circuit forming surface.

9. A semiconductor chip comprises:

a plurality of bonding pads, each bonding pad being formed on the integrated circuit forming surface;

a plurality of metal interconnects located on the integrated circuit forming surface of the chip and electrically connecting with the corresponding bonding pads;

a passivation layer covering the metal interconnects and having a plurality of the first openings and the second openings;

a plurality of test pads located at the first opening of the passivation layer, each conducting to the corresponding bonding pad through a corresponding metal interconnect; and

a plurality of contact pads located at the second opening of the passivation layer, wherein each contact pad connects in series with a metal interconnect between the corresponding bonding pad and test pad.

10. The semiconductor chip of claim 9, further comprising a plurality of flip chip bumps formed on the contact pads.

11. The semiconductor chip of claim 9, further comprising a plurality of test bumps formed on the test pads.

12. The semiconductor chip of claim 9, wherein the integrated circuit forming surface of the chip is rectangle and a plurality of test pads are arranged in zigzag pattern.

13. The semiconductor chip of claim 9, wherein the integrated circuit forming surface of the chip is rectangle and a plurality of test pads around the two corresponding sides of the integrated circuit forming surface.

14. The semiconductor chip of claim 9, wherein the integrated circuit forming surface of the chip is rectangle and the test pads around the perimeter of the integrated circuit forming surface.