SOI DRAM having P-doped poly gate for a memory pass transistor

• US 20020180069A1
• Filed: 05/09/2002
• Published: 12/05/2002
• Est. Priority Date: 05/24/1996
• Status: Active Grant

• Current Assignee: Theodore W. Houston
• Original Assignee: Theodore W. Houston
• Inventors: Houston, Theodore W.
• Granted Patent: US 6,703,673 B2
• Time in Patent Office: Days
• US Class Current: 257/202
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/0218 of field effect structures
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H10B 12/05 Making the transistor
• CPC Class Codes: H10B 12/09 with simultaneous manufacture of the peripheral circuit region and memory cells
• CPC Class Codes: H10B 12/50 Peripheral circuit region structures

Abstract

An integrated circuit including a DRAM is disclosed, wherein the DRAM includes a memory array including a plurality of pass gate transistors and a plurality of memory elements. The pass gate transistors include a gate material selected to provide a substantially near mid-gap work function or greater. The DRAM also includes a peripheral area including a plurality of logic transistors. In a preferred embodiment the pass gate transistors are silicon-on-insulator transistors.

Claims

1. An Integrated circuit including a DRAM, wherein said DRAM comprises:

a memory array including a plurality of pass gate transistors and a plurality of memory elements, wherein said pass gate transistors comprise a gate material selected to provide a substantially near mid-gap work function or greater; and

a peripheral area including a plurality of logic transistors.

2. The integrated circuit of claim 1 wherein said pass gate transistors are silicon-on-insulator transistors.

3. The integrated circuit of claim 1 wherein the gate material of said logic transistors is the same type of material as said gate material for said pass gate transistors.

4. The integrated circuit of claim 1 wherein said pass gate transistors are n-channel devices with p-doped polysilicon gate regions.

5. The integrated circuit of claim 1 wherein said pass gate transistors are p-channel devices with n-doped polysilicon gate regions.

6. The integrated circuit of claim 1 wherein said pass gate transistors are n-channel devices with titanium nitride gate regions.

7. The integrated circuit of claim 1 wherein said pass gate transistors are p-channel devices with titanium nitride gate regions.

8. The integrated circuit of claim 2 wherein said logic transistors are silicon-on-insulator transistors.

9. The integrated circuit of claim 2 wherein said pass gate transistors are fully depleted silicon-on-insulator transistors.

10. The integrated circuit of claim 8 wherein said pass gate transistors are fully depleted silicon-on-insulator transistors and said logic transistors comprise partially depleted silicon-on-insulator transistors.

11. The integrated circuit of claim 2 wherein the silicon film thickness for said pass gate transistors is thinner than the silicon film thickness for at least one of said logic transistors.

12. The integrated circuit of claim 10 wherein the silicon film thickness for said pass gate transistors is the same as the silicon film thickness for the logic transistors.

13. The integrated circuit of claim 1 wherein said pass gate transistors are inversion mode transistors.

14. The integrated circuit of claim 1 wherein said pass gate transistors are accumulation mode transistors.

15. The integrated circuit of claim 1 wherein said pass gate transistors are n-channel transistors and said logic transistors comprise n-channel transistors and p-channel transistors.

16. The integrated circuit of claim 1 wherein said pass gate transistors are n-channel transistors and said logic transistors comprise n-channel transistors and said logic transistors comprise n-channel transistors and p-channel transistors.

18. The integrated circuit of claim 17 wherein said pass gate transistors are p-channel transistors with N+doped polysilicon gate regions.

19. The integrated circuit of claim 17 wherein said P+doped polysilicon gate regions are clad with a metal layer.

20. The integrated circuit of claim 18 wherein said N+doped polysilicon gate regions are clad with a metal layer.

21. The integrated circuit of claim 19 wherein said metal layer comprises tungsten.

22. The integrated circuit of claim 20 wherein said metal layer comprises tungsten.

23. The integrated circuit of claim 17 wherein a silicide layer is formed on said P+polysilicon gate regions.

24. The integrated circuit of claim 18 wherein a silicide layer is formed on said N+polysilicon gate regions.

26. The integrated circuit of claim 25 wherein said pass gate transistors are p-channel devices with N+doped polysilicon gate regions.

27. The integrated circuit of claim 25 wherein said P+doped polysilicon gate regions are clad with a metal layer.

28. The integrated circuit of claim 26 wherein said N+doped polysilicon gate regions are clad with a metal layer.

29. The integrated circuit of claim 27 wherein said metal layer comprises tungsten.

30. The integrated circuit of claim 28 wherein said metal layer comprises tungsten.

31. The integrated circuit of claim 25 wherein a silicide layer is formed on said P+polysilicon gate regions.

32. The integrated circuit of claim 26 wherein a silicide layer is formed on said N+polysilicon gate regions.

17. An integrated circuit including a DRAM device, wherein said DRAM device comprises:

a memory array including a plurality of pass gate transistors and a plurality of memory elements, wherein said pass gate transistors comprise n-channel devices having P+doped polysilicon gate regions, wherein said pass gate transistors have fully depleted channel regions; and

a peripheral area including a plurality of logic transistors wherein said logic transistors have partially depleted channel regions.

25. An integrated circuit including a DRAM device, wherein said DRAM comprises:

a memory array including a plurality of pass gate transistors and a plurality of memory elements, wherein said pass gate transistors comprise n-channel devices having P+doped polysilicon gate regions; and

a peripheral area including a plurality of logic transistors.