Circuits and methods for synchronizing non-constant frequency switching regulators with a phase locked loop

• US 20020180413A1
• Filed: 07/15/2002
• Published: 12/05/2002
• Est. Priority Date: 04/06/2001
• Status: Active Grant

• Current Assignee: Analog Devices International Unlimited Company (Analog Devices, Inc.)
• Original Assignee: Linear Technology Corporation (Analog Devices, Inc.)
• Inventors: Flatness, Randy G., Umminger, Christopher B.
• Granted Patent: US 6,774,611 B2
• Time in Patent Office: Days
• US Class Current: 323/284
• CPC Class Codes: H02M 3/1584 with a plurality of power processing stages connected in parallel

Abstract

Methods for synchronizing non-constant frequency switching regulators with a phase locked loop are disclosed. The methods enable non-constant frequency switching regulators to be synchronized with a phase locked loop to achieve constant frequency operation in steady state while retaining the advantages of non-frequency operation to improve transient response and operate over a wider range of duty cycles. In addition, the methods enable multiple non-constant frequency regulators to be synchronized and operated in parallel to deliver higher power levels to the output than a single switching regulator.

Claims

1. A method for synchronizing a non-constant frequency switching regulator that generates a regulated voltage output at an output node, the method comprising:

providing a source voltage at an input node;

providing control circuitry coupled to the output node that controls the duty cycle of the switching regulator; and

providing a phase locked loop comprising a phase detector circuitry to control a parameter of the switching regulator, causing the switching frequency of the switching regulator to be constant.

2. The method of claim 1, wherein the switching regulator comprises a synchronous switching regulator.

3. The method of claim 1, wherein the switching regulator comprises a non-synchronous switching regulator.

4. The method of claim 1, wherein the switching regulator comprises a hysteretic switching regulator and the hysteresis is adjusted by the phase locked loop.

5. The method of claim 1, wherein the switching regulator comprises a constant on-time switching regulator, and the on-time is adjusted by the phase locked loop.

6. The method of claim 1, wherein the switching regulator comprises a constant off-time switching regulator, and the off-time is adjusted by the phase locked loop.

7. The method of claim 1, wherein the switching regulator comprises a step-down switching regulator.

8. The method of claim 1, wherein the switching regulator comprises a step-up switching regulator.

9. The method of claim 1, wherein the switching regulator comprises a buck-boost switching regulator.

10. The method of claim 1, further comprising

controlling the duty cycle of the switching regulator using current-mode control.

11. The method of claim 1, further comprising

controlling the duty cycle of the switching regulator using voltage-mode control.

12. The method of claim 1, further comprising

controlling the duty cycle of the switching regulator using a hybrid of current-mode and voltage-mode control.

13. The method of claim 1, wherein the switching regulator comprises a one shot timer having I_ON and V_ON inputs and an output to control the duty cycle of the switching regulator.

14. The method of claim 1, wherein the phase detector circuitry comprises:

a first rising edge triggered data flip flop;

a second rising edge triggered data flip flop;

an AND gate coupled between the first and the second flip flops;

an amplifier coupled between the second flip flop and the one shot timer of the switching regulator; and

a loop filter to extract the DC average value from the second flip flop.

16. The method of claim 15, wherein the plurality of switching regulators comprise synchronous and non-synchronous switching regulators.

17. The method of claim 15, wherein the plurality of switching regulators comprises one or more hysteretic switching regulators and the hysteresis is adjusted by the phase locked loop.

18. The method of claim 15, wherein the plurality of switching regulators comprises one or more constant on-time switching regulators, and the on-time is adjusted by the phase locked loop.

19. The method of claim 15, wherein the plurality of switching regulators comprises one or more constant off-time switching regulators, and the off-time is adjusted by the phase locked loop.

20. The method of claim 15, wherein the plurality of switching regulators comprises one or more step-down switching regulators.

21. The method of claim 15, wherein the plurality of switching regulators comprises one or more step-up switching regulators.

22. The method of claim 15, wherein the plurality of switching regulators comprises one of more buck-boost switching regulators.

23. The method of claim 15, further comprising

controlling the duty cycle of each switching regulator from the plurality of switching regulators using current-mode control.

24. The method of claim 15, further comprising

controlling the duty cycle of each switching regulator from the plurality of switching regulators using voltage-mode control.

25. The method of claim 15, further comprising

controlling the duty cycle of each switching regulator from the plurality of switching regulators using a hybrid of current-mode and voltage-mode control.

26. The method of claim 15, wherein each switching regulator from the plurality of switching regulators comprises a one shot timer having I_ON and V_ON inputs and an output to control the duty cycle of the switching regulator.

27. The method of claim 15, wherein the phase detector circuitry comprises:

a first rising edge triggered data flip flop;

a second rising edge triggered data flip flop;

an AND gate coupled between the first and the second flip flops;

an amplifier coupled between the second flip flop and the one shot timer of the first switching regulator; and

a loop filter to extract the DC average value from the second flip flop.

28. The method of claim 27, wherein the first flip flop comprises a clock input coupled to the output of the one shot timer of the first switching regulator.

29. The method of claim 27, wherein the second flip flop comprises a clock input coupled to the output of the one shot timer of the second switching regulator.

15. A method for synchronizing a plurality of non-constant frequency switching regulators, the method comprising:

providing a source voltage at a plurality of input nodes;

providing a regulated voltage at a plurality of output nodes;

providing control circuitry coupled to the plurality of output nodes to control the duty cycles of the plurality of regulators; and

providing a plurality of phase locked loops, each phase locked loop from the plurality of phase locked loops coupled between a first and a second switching regulators selected from the plurality of switching regulators, wherein each phase locked loop comprises phase detector circuitry to control the on-time of the first switching regulator, causing the switching frequency of the first and second switching regulators to be equal.

30. A method for adjusting the switching frequency of a non-constant frequency switching regulator, the method comprising:

providing a one shot timer in the switching regulator comprising I_ON and V_ON inputs and an output to control the duty cycle of the switching regulator;

providing a phase locked loop connected to the I_ON or V_ON input and the output of the one shot timer to control the on-time of the one shot timer, causing the steady state switching frequency of the switching regulator to be constant.

31. The method of claim 30, wherein the phase locked loop comprises:

a first rising edge triggered data flip flop;

a second rising edge triggered data flip flop;

an AND gate coupled between the first and the second flip flops;

an amplifier coupled between the second flip flop and the one shot timer of the first switching regulator; and

a loop filter to extract the DC average value from the second flip flop.

32. The method of claim 31, wherein the first flip flop comprises a clock input coupled to a reference clock.

33. The method of claim 31, wherein the second flip flop comprises a clock input coupled to the output of the one shot timer.

34. The method of claim 30, wherein the switching regulator comprises a synchronous switching regulator.

35. The method of claim 30, wherein the switching regulator comprises a non-synchronous switching regulator.

36. The method of claim 30, wherein the switching regulator comprises a hysteretic switching regulator and the hysteresis is adjusted by the phase locked loop.

37. The method of claim 30, wherein the switching regulator comprises a constant on-time switching regulator, and the on-time is adjusted by the phase locked loop.

38. The method of claim 30, wherein the switching regulator comprises a constant off-time switching regulator, and the off-time is adjusted by the phase locked loop.

39. The method of claim 30, wherein the switching regulator comprises a step-down switching regulator.

40. The method of claim 30, wherein the switching regulator comprises a step-up switching regulator.

41. The method of claim 30, wherein the switching regulator comprises a buck-boost switching regulator.

42. The method of claim 30, further comprising

controlling the duty cycle of the switching regulator using current-mode control.

43. The method of claim 30, further comprising

controlling the duty cycle of the switching regulator using voltage-mode control.

44. The method of claim 30, further comprising

controlling the duty cycle of the switching regulator using a hybrid of current-mode and voltage-mode control.

46. The circuit of claim 45, wherein the phase locked loop comprises:

a first rising edge triggered data flip flop;

a second rising edge triggered data flip flop;

an AND gate coupled between the first and the second flip flops;

an amplifier coupled between the second flip flop and the one shot timer; and

a loop filter to extract the DC average value from the second flip flop.

47. The circuit of claim 46, wherein the first flip flop comprises a clock input coupled to a reference clock.

48. The circuit of claim 46, wherein the second flip flop comprises a clock input coupled to the output of the one shot timer.

49. The circuit of claim 45, wherein the switching regulator comprises a synchronous switching regulator.

50. The circuit of claim 45, wherein the switching regulator comprises a non-synchronous switching regulator.

51. The circuit of claim 45, wherein the switching regulator comprises a hysteretic switching regulator and the hysteresis is adjusted by the phase locked loop.

52. The circuit of claim 45, wherein the switching regulator comprises a constant on-time switching regulator, and the on-time is adjusted by the phase locked loop.

53. The circuit of claim 45, wherein the switching regulator comprises a constant off-time switching regulator, and the off-time is adjusted by the phase locked loop.

54. The circuit of claim 45, wherein the switching regulator comprises a step-down switching regulator.

55. The circuit of claim 45, wherein the switching regulator comprises a step-up switching regulator.

56. The circuit of claim 45, wherein the switching regulator comprises a buck-boost switching regulator.

57. The circuit of claim 45, further comprising controlling the duty cycle of the switching regulator using current-mode control.

58. The circuit of claim 45, further comprising controlling the duty cycle of the switching regulator using voltage-mode control.

59. The circuit of claim 45, further comprising controlling the duty cycle of the switching regulator using a hybrid of current-mode and voltage-mode control.

45. A circuit for adjusting the switching frequency of a non-constant frequency switching regulator having a one shot timer comprising I_ON and V_ON inputs and an output to control the duty cycle of the switching regulator, the one shot timer coupled between an input voltage and a regulated output voltage, the circuit comprising:

a phase locked loop connected to the I_ON or V_ON input and the output of the one shot timer to control the on-time of the one shot timer, causing the steady state switching frequency of the switching regulator to be constant.

60. A circuit for synchronizing a plurality of non-constant frequency switching regulators, each switching regulator from the plurality of switching regulators having a one shot timer comprising I_ON and V_ON inputs and an output to control the duty cycle of the switching regulator, the one shot timer coupled between an input voltage and a regulated output voltage, the circuit comprising:

a plurality of phase locked loops, each phase locked loop from the plurality of phase locked loops coupled between the one shot timer of a first switching regulator and the one shot timer of a second switching regulator selected from the plurality of switching regulators, wherein each phase locked loop controls the on-time of the first switching regulator, causing the switching frequency of the first and second switching regulators to be equal.

61. The circuit of claim 60, wherein the plurality of switching regulators comprise synchronous and non-synchronous switching regulators.

62. The circuit of claim 60, wherein the plurality of switching regulators comprises one or more hysteretic switching regulators and the hysteresis is adjusted by the phase locked loop.

63. The circuit of claim 60, wherein the plurality of switching regulators comprises one or more constant on-time switching regulators, and the on-time is adjusted by the plurality of phase locked loops.

64. The circuit of claim 60, wherein the plurality of switching regulators comprises one or more constant off-time switching regulators, and the off-time is adjusted by the plurality of phase locked loops.

65. The circuit of claim 60, wherein the plurality of switching regulators comprises one or more step-down switching regulators.

66. The circuit of claim 60, wherein the plurality of switching regulators comprises one or more step-up switching regulators.

67. The method of claim 60, wherein the plurality of switching regulators comprises one or more buck-boost switching regulators.

68. The circuit of claim 60, further comprising controlling the duty cycle of each switching regulator from the plurality of switching regulators using current-mode control.

69. The circuit of claim 60, further comprising controlling the duty cycle of each switching regulator from the plurality of switching regulators using voltage-mode control.

70. The circuit of claim 60, further comprising controlling the duty cycle of each switching regulator from the plurality of switching regulators using a hybrid of current-mode and voltage-mode control.

71. The circuit of claim 60, wherein each phase locked loop from the plurality of phase locked loops comprises:

a first rising edge triggered data flip flop;

a second rising edge triggered data flip flop;

an AND gate coupled between the first and the second flip flops;

an amplifier coupled between the second flip flop and the one shot timer of the first switching regulator; and

a loop filter to extract the DC average value from the second flip flop.

72. The circuit of claim 71, wherein the first flip flop comprises a clock input coupled to the output of the one shot timer of the first switching regulator.

73. The circuit of claim 71, wherein the second flip flop comprises a clock input coupled to the output of the one shot timer of the second switching regulator.