Contactless integrated circuit comprising a wired logic anticollision circuit

• US 20020180487A1
• Filed: 04/03/2002
• Published: 12/05/2002
• Est. Priority Date: 04/04/2001
• Status: Active Grant

• Current Assignee: STMicroelectronics SA (STMicroelectronics NV)
• Original Assignee: STMicroelectronics SA (STMicroelectronics NV)
• Inventors: Kari, Ahmed, Moreaux, Christophe
• Granted Patent: US 6,779,091 B2
• Time in Patent Office: Days
• US Class Current: 326/136
• CPC Class Codes: G06K 19/0723 the record carrier comprising an arrangement for non-contact communication, e.g. wireless communication circuits on transponder cards, non-contact smart cards or RFIDs
• CPC Class Codes: G06K 7/10019 resolving collision on the communication channels between simultaneously or concurrently interrogated record carriers. collision between the communication channels used by wireless communication devices, where the solution is not particularly adapted for RFIDs or the like, H04W74/08
• CPC Class Codes: G06K 7/10346 the antenna being of the far field type, e.g. HF types or dipoles
• CPC Class Codes: G07C 9/28 the pass enabling tracking or indicating presence

Abstract

An integrated circuit having an identification code of M bits includes a communication interface circuit for receiving a selective identification request and a selection code, and a processing circuit connected thereto. The processing circuit includes a logic comparator having a first input for receiving the selection code and a second input for receiving the identification code, and an output for delivering an equal signal if the selection and identification codes are equal. A shift register has an output coupled to the first input of the logic comparator. A serial memory stores the identification code, and has a serial output coupled to the second input of the logic comparator and to a serial input of the shift register. A controller is connected to the shift register and to the serial memory for loading the selection code into the shift register, and for applying M shift pulses to the shift register and M read pulses to the serial memory. An inhibiting circuit inhibits the logic comparator when N shift and read pulses have been applied to the shift register and to the serial memory.

Claims

1. Integrated circuit (CIC) comprising an identification code (ID) of M bits and means for processing a selective identification request (INVENTORY) accompanied with a selection code (MV), characterized in that the processing means comprise:

a shift register (SREG) comprising a serial output (ROUT) coupled to a first input (CIN1) of a logic comparator (SCOMP),

a serial memory (SMEM) containing the identification code (ID) and comprising a serial output (MOUT) coupled to a second input (CIN2) of the comparator and to a serial input (RIN) of the shift register,

means (CNTR) for loading, into the shift register (SREG), a received selection code (MV),

means (CNTR) for applying M shift pulses (CK1) to the shift register and M read pulses (READ) to the memory,

means (MLCT, A2) for inhibiting the comparator when N shift and read pulses have been applied to the register and the memory, and

means for delivering to a communication interface (ADC, RFI) of the integrated circuit, at a predetermined time (t7), data present in the shift register, if the comparator delivers an equality signal (EQ=1).

2. Integrated circuit according to claim 1, wherein the means for inhibiting the comparator comprise a first counting circuit (MLCT) arranged to count the number N in synchronism with the shift (CK1) and read (READ) pulses, and to deliver an inhibition signal (STOP) of the comparator when number N is counted.

3. Integrated circuit according to claim 2, wherein the first counting circuit (MLCT) comprises:

a down-counter (DCT1),

means (CNTR, LOAD) for loading number N (ML) into the down-counter, and

a logic circuit (NO1) for delivering the inhibition signal (STOP) when the down-counter reaches the value zero.

4. Integrated circuit according to one of the claims 2 and 3, wherein the means (A2, EQ) for inhibiting the comparator are also arranged to inhibit the comparator when the comparator delivers an inequality signal (EQ=0).

5. Integrated circuit according to one of the claims 2 to 4, wherein the means (MLCT, A2) for inhibiting the comparator are also arranged to inhibit the first counting circuit (MLCT) when the comparator delivers an inequality signal (EQ=0).

6. Integrated circuit according to one of the claims 2 to 5, wherein the comparator comprises synchronous latches (D1, D2, D3) driven by a signal (DEC) synchronized with the shift (CK1) and read (READ) pulses.

7. Integrated circuit according to claim 6, wherein the means for inhibiting the comparator comprise a logic gate (A2) for blocking the synchronization signal (DEC) of the comparator'"'"'s latches.

8. Integrated circuit according to one of the claims 1 to 7, wherein the means for delivering data present in the shift register to the communication interface of the integrated circuit comprise:

means (CNTR, TRANSEN, A3) for coupling a serial output of the shift register to the communication interface (ADC, RFI) of the integrated circuit when an authorization signal (TRANSEN1) is delivered,

means (TSCT) for delivering the authorization signal (TRANSEN1) at the latest when the predetermined time is reached, and

means (NO2, I3) for preventing the delivery of the authorization signal when the output of the comparator presents an inequality value.

9. Integrated circuit according to claim 8, wherein the means for delivering the authorization signal comprise:

a second counting circuit (TSCT) arranged to count a number P (ML) and to deliver the authorization signal when number P is counted, and

a controller (CNTR) for applying, to the counting circuit, a counting signal by one unit (NTS) at each reception, by the integrated circuit, of a response request (EOF) to the selective identification request.

10. Integrated circuit according to claim 9, wherein the second counting circuit (TSCT) comprises:

a down-counter (DCT2),

means (CNTR, A5, CK1) for loading number P into the down-counter, and

means (NO2) for delivering the authorization signal (TRANSEN1) when the down-counter reaches the value zero.

11. Integrated circuit according to claim 10, wherein the means for loading number P into the down-counter are arranged to start the loading of number P after the application of N shift pulses (CK1) to the shift register and N read pulses (READ) to the memory, if the comparator does not deliver an inequality signal (EQ=0).

12. Integrated circuit according to one of the claims 10 and 11, wherein the means for loading number P into the down-counter comprise means for bit by bit loading L bits of the identification code (ID) delivered by the memory (SMEM) after N read pulses.

13. Integrated circuit according to claim 12, wherein the means for loading L bits of the identification code into the down-counter comprise a counter (BCT) arranged to count L one bit loading cycles and means (A5) for inhibiting the loading of the down-counter (DCT2) when number L is reached.

14. Integrated circuit according to one of the claims 1 to 13, wherein the shift register (SREG) also comprises a parallel input for receiving the selection code (MV, MV0-MV7).

15. Integrated circuit according to one of the claims 1 to 14, wherein the shift register (SREG) comprises at least two shit registers (SREG0-SREG7) arranged in parallel having serial inputs coupled to a demultiplexer (DMUX) and serial outputs coupled to a multiplexer (MUX).

16. Integrated circuit according to one of the claims 1 to 15, comprising a contactless communication interface (RFI) operating with inductive coupling.

17. Integrated circuit according to one of the claims 1 to 16, arranged to process a selective identification request INVENTORY provided by the ISO/IEC/FCD 15693-3 standard.

18. Portable electronic device of the chip card type, electronic label type or analogue, comprising an integrated circuit according to one of the claims 1 to 17.

20. Method according to claim 19, comprising a step of down-counting the number N by means of a first down-counter (MLCT, DCT1) in which number N (ML) is loaded, and a step of delivering an inhibition signal (STOP) of the comparator when zero is reached.

26. Method according to one of the claims 20 to 25, wherein the shift register is designed with at least two shit registers (SREG0-SREG7) arranged in parallel, having serial inputs coupled to a demultiplexer (DMUX) and serial outputs (MUX) coupled to a multiplexer.

27. Method according to one of the claims 20 to 26, implemented for processing an INVENTORY command provided by the ISO/IEC/FCD 15693-3 standard.

19. Method of processing, in an integrated circuit (CIC) to which is allocated an identification code (ID), a selective identification request (INVENTORY) accompanied with a selection code (MV), characterized in that it comprises the following steps:

providing a shift register (SREG), a serial memory (SMEM) and a logic comparator (SCOMP),

storing the identification code (ID) of the integrated circuit in the serial memory,

loading the received selection code (MV) into the shift register,

coupling a serial output (ROUT) of the shift register to a first input (CIN1) of a logic comparator,

coupling a serial output (MOUT) of the memory to a second input (CIN2) of the comparator and to a serial input (RIN) of the shift register,

applying M shift pulses to the shift register and M read pulses to the memory,

inhibiting the comparator when N shift and read pulses have been applied to the register and the memory, and

delivering data present in the shift register to a communication interface (ADC, RFI) of the integrated circuit, at a predetermined time (t7), if the comparator delivers an equality signal (EQ).

21. Method according to one of the claims 19 and 20, comprising a step of early inhibition of the comparator when the comparator delivers an inequality signal (EQ=0).

22. Method according to one of the claims 19 to 22, wherein the step of delivering data present in the shift register to the communication interface comprises the connection of an output (ROUT) of the shift register to the communication interface of the integrated circuit (ADC, RFI) when an authorization signal (TRANSEN1) is delivered, and the delivery of the authorization signal (TRANSEN1=1) at the latest when the predetermined time is reached, except if the comparator delivers an inequality signal (EQ=0).

23. Method according to claim 22, wherein the authorization signal is delivered by means of a second down-counter (TSCT, DCT2) provided for counting a number P, the authorization signal being delivered when the down-counter reaches zero, a down-counting signal by one unit (ST) being applied to the second down-counter at each reception, by the integrated circuit, of a response request (EOF) to the selective identification request.

24. Method according to claim 23, comprising a step of loading number P into the second down-counter after the application of N shift pulses to the shift register and N read pulses to the memory, performed if the comparator does not deliver an inequality signal (EQ=0).

25. Method according to claim 24, wherein the loading of number P into the second down-counter comprises the bit by bit loading, into the second down-counter, of L bits of the identification code (ID) delivered by the memory after the application of N read pulses (READ).