Efficient pulse amplitude modulation transmit modulation

• US 20020180547A1
• Filed: 05/22/2002
• Published: 12/05/2002
• Est. Priority Date: 05/23/2001
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Leipold, Dirk, Staszewski, Robert B., Maggio, Kenneth J.
• Granted Patent: US 6,924,681 B2
• Time in Patent Office: Days
• US Class Current: 332/115
• CPC Class Codes: H03F 1/02 Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
• CPC Class Codes: H03F 1/0205 in transistor amplifiers
• CPC Class Codes: H03F 2200/331 Sigma delta modulation being used in an amplifying circuit
• CPC Class Codes: H03F 3/217 Class D power amplifiers; Switching amplifiers
• CPC Class Codes: H03F 3/2171 with field-effect devices H03F3/2173 - H03F3/2178 take precedence
• CPC Class Codes: H03F 3/2176 Class E amplifiers
• CPC Class Codes: H03K 5/06 by the use of delay lines or other analogue delay elements
• CPC Class Codes: H03K 7/02 Amplitude modulation, i.e. PAM
• CPC Class Codes: H04B 1/0483 Transmitters with multiple parallel paths
• CPC Class Codes: H04B 2001/0491 with frequency synthesizers, frequency converters or modulators

Abstract

Efficient PAM transmit modulation is provided by a PAM modulator that includes an oscillator (404) that provides a clock signal, CKV, (408). The clock signal 408 and a delayed version (CKV_DLY) 420 of the clock signal are provided to a logic gate (414). The output of logic gate (414) is used as a power amplifier input signal (PA_IN) for radio frequency power amplifier (416). Depending on the relative time delay of the CKV clock signal (408) and the CKV_DLY delayed clock signal (420), the timing and duty cycle of the logic gate (414) duty cycle can be controlled. The duty cycle or pulse-width variation affects the turn-on time of the power amplifier (416); thereby establishing the RF output amplitude.

Claims

1. A pulse amplitude modulator, comprising:

an oscillator for providing a clock signal;

a delay circuit having an input for receiving the clock signal and an output for providing a delayed version of the clock signal;

a logic circuit having inputs for receiving both the clock signal and the delayed version of the clock signal and having an output for providing a power amplifier input signal.

2. A pulse amplitude modulator as defined in claim 1, further comprising:

a power amplifier having an input port for receiving the power amplifier input signal.

3. A pulse amplitude modulator as defined in claim 1, wherein the delay circuit has a delay control input for receiving a delay control signal.

4. A pulse amplitude modulator as defined in claim 3, wherein the delay control signal comprises an analog signal.

5. A pulse amplitude modulator as defined in claim 3, wherein the delay control signal controls the amount of delay provided by the delay circuit.

6. A pulse amplitude modulator as defined in claim 1, wherein the delay circuit comprises a plurality of serially connected inverters or a plurality of serially connected buffers.

7. A pulse amplitude modulator as defined in claim 1, wherein the delay circuit comprises a delay line having a plurality of delay taps.

8. A pulse amplitude modulator as defined in claim 1, wherein the oscillator comprises a digitally controlled oscillator (DCO).

9. A pulse amplitude modulator as defined in claim 2, wherein the radio frequency power amplifier provides a radio frequency output signal whose amplitude is established by the amount of delay provided by the delay circuit.

10. A pulse amplitude modulator as defined in claim 3, wherein the delay circuit comprises a plurality of serially connected delay stages which are controlled using the delay control signal which comprises a delay control word having a plurality of bits, and each one of the bits controlling one of the serially connected delay stages.

11. A pulse amplitude modulator as defined in claim 3, wherein the delay circuit comprises a plurality of controllable serially connected delay stages, with the delay stages having a binary-weighted or unit-weighted arrangement.

12. A pulse amplitude modulator as defined in claim 3, wherein the delay control signal is synchronized with the CKV signal in order to avoid changing the delay control signal while the signal is still propagating through the delay circuit.

13. A pulse amplitude modulator as defined in claim 3, wherein the delay circuit comprises a high-speed delay dithering circuit and a low-speed delay dithering circuit.

14. A pulse amplitude modulator as defined in claim 13, wherein the high-speed dithering circuit and the low-speed dithering circuits are coupled in series.

15. A pulse amplitude modulator as defined in claim 2, wherein the power amplifier includes a plurality of digitally controlled switches that provide for amplitude modulation adjustment.

16. A pulse amplitude modulator as defined in claim 15, wherein the plurality of digitally controlled switches comprise a plurality of parallel connected transistors.

17. A pulse amplitude modulator as defined in claim 1, wherein the oscillator comprises a digitally controlled oscillator (DCO) having an input and further comprising a tuning word adjustment circuit coupled to the input of the DCO, the tuning word adjustment circuit changes the DCO frequency for a single clock cycle.

19. A transmitter circuit as defined in claim 18, wherein the delay circuit has a delay control input for receiving a delay control signal.

20. A transmitter circuit as defined in claim 19, wherein the delay control signal comprises an analog signal.

21. A transmitter circuit as defined in claim 19, wherein the delay control signal controls the amount of delay provided by the delay circuit.

22. A transmitter circuit as defined in claim 18, wherein the delay circuit comprises a delay line having a plurality of delay taps.

23. A transmitter circuit as defined in claim 18, wherein the oscillator comprises a digitally controlled oscillator (DCO).

24. A transmitter circuit as defined in claim 18, wherein the power amplifier provides a radio frequency output signal whose amplitude is established by the amount of delay provided by the delay circuit.

25. A transmitter circuit as defined in claim 18, wherein the delay circuit comprises a plurality of serially connected inverters or buffers.

26. A transmitter as defined in claim 18, wherein the power amplifier includes a plurality of digitally controlled switches that provide for amplitude modulation adjustment.

27. A transmitter circuit as defined in claim 26, wherein the plurality of digitally controlled switches comprise a plurality of parallel connected transistors.

28. A transmitter circuit as defined in claim 18, wherein the oscillator comprises a digitally controlled oscillator (DCO) having an input and further comprising a tuning word adjustment circuit coupled to the input of the DCO, the tuning word adjustment circuit changes the DCO frequency for a single clock cycle.

29. A transmitter circuit as defined in claim 28, wherein the DCO frequency is performed during update intervals determined by a reference clock signal provided to the tuning word adjustment circuit.

18. A transmitter circuit, comprising:

a pulse amplitude modulator (PAM) including;

an oscillator for providing a clock signal;

a delay circuit having an input for receiving the clock signal and an output for providing a delayed version of the clock signal; and

a logic circuit having inputs for receiving both the clock signal and the delayed version of the clock signal and having an output for providing a power amplifier input signal; and

a digitally controlled power amplifier responsive to the power amplifier input signal.