Display device

• US 20020180675A1
• Filed: 04/11/2002
• Published: 12/05/2002
• Est. Priority Date: 05/30/2001
• Status: Active Grant

• Current Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Hirano, Nobuyuki, Tobita, Youichi, Agari, Masafumi
• Granted Patent: US 7,006,067 B2
• Time in Patent Office: Days
• US Class Current: 345/87
• CPC Class Codes: G09G 2300/0842 forming a memory circuit, e.g. a dynamic memory with one capacitor
• CPC Class Codes: G09G 2310/0213 controlling the sequence of the scanning lines with respect to the patterns to be displayed, e.g. to save power
• CPC Class Codes: G09G 2310/0248 Precharge or discharge of column electrodes before or after applying exact column voltages
• CPC Class Codes: G09G 2310/08 Details of timing specific for flat panels, other than clock recovery
• CPC Class Codes: G09G 2330/022 in absence of operation, e.g. no data being entered during a predetermined time
• CPC Class Codes: G09G 3/006 Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays testing individual LED's G01R31/2635; testing lamps G01R31/44; testing of optical features of LCD displays G02F1/1309
• CPC Class Codes: G09G 3/20 for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
• CPC Class Codes: G09G 3/3208 organic, e.g. using organic light-emitting diodes [OLED]
• CPC Class Codes: G09G 3/3233 with pixel circuitry controlling the current through the light-emitting element
• CPC Class Codes: G09G 3/3618 with automatic refresh of the display panel using sense/write circuits
• CPC Class Codes: G09G 3/3648 using an active matrix G09G3/367 - G09G3/3696 take precedence
• CPC Class Codes: G09G 3/3677 suitable for active matrices only
• CPC Class Codes: G09G 3/3688 suitable for active matrices only

Abstract

Complementary signal lines are provided for data lines provided corresponding to columns of pixels arranged in a display pixel matrix. In a refresh mode, data of these pixels are read out on the complementary signal lines CL and CR, and differentially amplified by a sense amplifier, and the data differentially amplified is written in the original pixel. A refreshing operation is carried out internally and there is no need for externally providing a refreshing memory for storing data used in refreshing the pixel data. Thus, it is possible to reduce the current consumption for holding data of pixels.

Claims

1. A display device comprising:

a plurality of pixel elements arranged in rows and columns;

a plurality of scanning lines, arranged corresponding to the respective rows, each for transmitting a selection signal to pixel elements in a corresponding row;

a plurality of data lines, arranged corresponding to said columns, each for transmitting a data signal to pixel elements on a corresponding column;

a plurality of selection transistors, arranged corresponding to the respective pixel elements, each for transmitting a data signal on a corresponding data line to a corresponding pixel element in response to a selection signal on a corresponding scanning line;

holding capacitance elements, arranged corresponding to the respective selection transistors, each for holding a voltage applied to a corresponding pixel element; and

refresh circuitry for reading out holding voltages of the holding capacitance elements in response to a refresh instruction, and refreshing the holding voltages of the holding capacitance elements in accordance with a read out holding voltage signals.

2. The display device according to claim 1, wherein the data lines are arranged in pairs, and said refresh circuitry comprises:

a data line control circuit for connecting the data lines to pairs of complementary signal lines arranged corresponding to the respective pairs of data lines in response to said refresh instruction;

a voltage setting circuit selectively activated in response to said refresh instruction, for setting said paired complementary signal lines to a predetermined voltage level when activated;

a differential amplification circuit, provided corresponding to each pair of complementary signal lines and selectively activated in response to said refresh instruction, for differentially amplifying the voltages of corresponding pair of complementary signal lines when activated; and

row selection circuit for driving the scanning lines to a selected state in a predetermined order in response to said refresh instruction and coupling the holding capacitance elements on a selected row to corresponding data lines.

3. The display device according to claim 1, wherein the data lines are arranged in pairs, and said refresh circuitry comprises:

refresh request circuit for generating a refresh request in response to said refresh instruction at predetermined intervals;

a data line control circuit responsive to said refresh instruction, for selectively connecting the data lines in pairs to pairs of complementary signal lines arranged corresponding to the columns, complementary signal lines in a pair generating complementary signals;

a voltage initial setting circuit, provided corresponding to said pairs of complementary signal lines, for setting corresponding pairs of complementary signal lines to a predetermined voltage level when activated;

a differential amplification circuit, each arranged corresponding to the pair of the complementary signal lines, for differentially amplifying potentials of a corresponding pair of complementary signal lines when activated;

line selection circuit responsive to said refresh request signal, for selecting said plurality of scanning lines in a predetermined order and connecting the holding capacitance elements on a selected row to corresponding data lines; and

a refresh control circuit responsive to said refresh request signal, for selectively activating said voltage initial setting circuit and said differential amplification circuit.

4. The display device according to claim 1, wherein

the data lines comprises a pair of a first internal data line and a second internal data line arranged corresponding to each column of pixel elements and transmitting complementary signals,

said pixel elements are arranged corresponding to crossing sections between each of the scanning lines and one of the first and second data lines in each column.

5. The display device according to claim 2, wherein

two scanning lines are arranged in each row;

the data lines are arranged corresponding to the respective columns of the pixel elements;

with respect to pixel elements on each row, the pixel elements on adjacent columns are connected to different scanning lines, and data lines on the adjacent columns are arranged forming a pair; and

said data line control circuit connects the data lines in pairs to the pairs of complementary signal lines;

upon activation of said refresh instruction, said row selection circuit selects a scanning line in a selected row so that the holding capacitance element is connected to one data line of the data lines in a pair; and

upon non-activation of said refresh instruction, said row selection circuit simultaneously selects two scanning lines in the selected row.

6. The display device according to claim 5 further comprising:

reference capacitance elements each connected to a data line different from the data line connected to a pixel element in the data lines in a pair in each row when selected, for holding a voltage corresponding complementary data to a corresponding holding capacitance element.

7. The display device according to claim 3, wherein

two scanning lines are arranged in each row;

data lines are arranged corresponding to the respective columns of the pixel elements;

with respect to pixel elements on each row, the pixel elements on adjacent columns are connected to different scanning lines, and the data lines on the adjacent columns are arranged forming a pair;

said data line control circuit connects the data lines in pairs to said pairs of complementary signal lines; and

upon activation of said refresh instruction, said row selection circuit selects one scanning line in a selected row so that the holding capacitance element is connected to one data line of the data lines in a pair, and upon inactivation of said refresh instruction, said row selection circuit simultaneously selects two scanning lines in the selected row.

8. The display device according to claim 7 further comprising:

reference capacitance elements each connected to a data line different from the data line connected to a pixel element in data lines in a pair in each row when selected, and holding a voltage corresponding complementary data to a corresponding holding capacitance element.

9. The display device according to claim 1, wherein each of the pixel elements includes a driving transistor selectively rendered conductive in accordance with a holding voltage of a corresponding holding capacitance element, for coupling a common electrode to a corresponding pixel electrode, and a liquid crystal element provided between said pixel electrode and a counter electrode.

10. The display device according to claim 2, wherein said refresh circuitry further comprises:

an inversion writing circuit for inverting a data signal amplified by the differential amplification circuit of a pair of complementary signal lines for writing into a corresponding voltage holding capacitance element; and

a polarity inversion circuit for inverting a polarity of a voltage to be applied to a counter electrode of the pixel element.

11. The display device according to claim 10, wherein said refresh circuitry inverts the polarity of the voltage of the counter electrode of said pixel element, upon completion of a refreshing of the holding voltage with respect to all said pixel elements once.

12. The display device according to claim 3, wherein said refresh circuitry further comprises:

an inversion writing circuit for inverting a data signal amplified by the differential amplification circuit on a pair of the complementary signal lines for storage into a corresponding voltage holding capacitance element; and

a polarity inversion circuit for inverting a polarity of a voltage to be applied to a counter electrode of the pixel element associated with said corresponding capacitance element.

13. The display device according to claim 12, wherein, when a refreshing of the holding voltage is completed once with respect to all said pixel elements, said refresh circuitry inverts the voltage polarity of the counter electrode of the pixel element.

14. The display device according to claim 12, wherein said pixel element comprises a liquid crystal element receiving the holding voltage of a corresponding holding capacitance element on one electrode thereof.

15. The display device according to claim 1, wherein said pixel element comprises an element being supplied with a current in accordance with the holding voltage of a corresponding holding capacitance element for emitting light.

16. The display device according to claim 1, wherein

said plurality of data lines are provided with adjacent data lines forming a pair;

said refresh circuitry connects the holding capacitance element to one of the data lines in a corresponding pair upon activation of said refresh instruction, for refreshing the holding voltage of the holding capacitance element connected to the one of the data lines, and connects the holding capacitance element to both of the data lines in the pair in a normal operation mode for storing data transmitted through the data lines in said holding capacitance elements.

17. The display device according to claim 16, further comprising:

a test output circuit for externally transmitting voltage signals of data lines in a pair.

18. The display device according to claim 17, further comprising:

an amplification circuit for amplifying a voltage signal read out from said voltage holding capacitance element on a data line of data lines in a pair, and

said test output circuit externally outputs the voltage signal amplified by the amplification circuit.

19. The display device according to claim 1, further comprising reference cells arranged corresponding to the respective holding capacitance elements, for storing complementary data to data of corresponding holding capacitance elements.

20. The display device according to claim 19, wherein the reference cells are aligned in a row direction with corresponding holding capacitance elements.