Electronic system and method for display using a decoder and arbiter to selectively allow access to a shared memory

• US 20020180743A1
• Filed: 06/19/2002
• Published: 12/05/2002
• Est. Priority Date: 08/26/1996
• Status: Active Grant

• Current Assignee: Parthenon Unified Memory Architecture LLC (Acacia Research Corporation)
• Original Assignee: STMicroelectronics Incorporated (STMicroelectronics NV)
• Inventors: Colavin, Osvaldo, Owen, Jefferson Eugene, Diaz, Raul Zegers
• Granted Patent: US 7,321,368 B2
• Time in Patent Office: Days
• US Class Current: 345/541
• CPC Class Codes: G06F 13/1605 based on arbitration arbitration in handling access to a common bus or bus system G06F13/36
• CPC Class Codes: G06F 13/18 based on priority control G06F13/1605 takes precedence
• CPC Class Codes: G06F 15/167 using a common memory, e.g. mailbox
• CPC Class Codes: G06T 1/60 Memory management
• CPC Class Codes: G09G 2340/02 Handling of images in compressed format, e.g. JPEG, MPEG
• CPC Class Codes: G09G 2360/18 Use of a frame buffer in a display terminal, inclusive of the display panel
• CPC Class Codes: G09G 5/001 Arbitration of resources in a display system, e.g. control of access to frame buffer by video controller and/or main processor
• CPC Class Codes: G09G 5/363 Graphics controllers
• CPC Class Codes: H04N 19/423 characterised by memory arrangements H04N19/433 takes precedence
• CPC Class Codes: H04N 19/427 Display on the fly, e.g. simultaneous writing to and reading from decoding memory
• CPC Class Codes: H04N 19/61 in combination with predictive coding
• CPC Class Codes: H04N 21/443 OS processes, e.g. booting an STB, implementing a Java virtual machine in an STB or power management in an STB
• CPC Class Codes: H04N 21/4435 Memory management allocation of memory to service a request G06F9/5016; addressing or allocating within memory systems or architectures G06F12/02

Abstract

An electronic system, an integrated circuit and a method for display are disclosed. The electronic system contains a first device, a memory and a video/audio compression/decompression device such as a decoder/encoder. The electronic system is configured to allow the first device and the video/audio compression/decompression device to share the memory. The electronic system may be included in a computer in which case the memory is a main memory. Memory access is accomplished by one or more memory interfaces, direct coupling of the memory to a bus, or direct coupling of the first device and decoder/encoder to a bus. An arbiter selectively provides access for the first device and/or the decoder/encoder to the memory. The arbiter may be monolithically integrated into a memory interface. The decoder may be a video decoder configured to comply with the MPEG-2 standard. The memory may store predicted images obtained from a preceding image.

Claims

1. An electronic system comprising coupled to a memory comprising:

a display device;

a fast bus; and

a decoder coupled to the fast bus for receiving compressed images and displaying the decoded images on the display device;

the decoder coupled to the memory storing at least one previously decoded image used to decode a current image, wherein the memory is a region of a main memory of the computer, accessible through the fast bus.

2. An electronic system according to claim 1, wherein the decoder directly supplies a display adapter of the display device with an image under decoding which is not used to decode a subsequent image.

3. An electronic system according to claim 1, wherein the memory stores intra images which are not obtained from a preceding image and predicted images which are obtained from a single preceding image, the images directly supplied to the display adapter being bidirectional images obtained from two preceding intra or predicted images.

4. An electronic system according to claim 1, wherein the decoder is integrated into a computer motherboard.