Image processing apparatus implemented in IC chip

• US 20020181597A1
• Filed: 05/24/2002
• Published: 12/05/2002
• Est. Priority Date: 06/01/2001
• Status: Active Grant

• Current Assignee: Godo Kaisha IP Bridge 1 (IP Bridge, Inc.)
• Original Assignee: Sanyo Electric Company Limited (Panasonic Holdings Corporation)
• Inventors: Okada, Shigeyuki
• Granted Patent: US 7,065,141 B2
• Time in Patent Office: Days
• US Class Current: 375/240.25
• CPC Class Codes: H04N 5/783 Adaptations for reproducing at a rate different from the recording rate
• CPC Class Codes: H04N 9/8042 involving data reduction

Abstract

When a reverse reproduction is instructed, an MPEG video stream is once decoded and is converted to image video signals by a first display circuit. Thereafter, the image video signals are again recoded by an image input circuit and an MPEG video encoder, so as to be overwritten in a storage area of a hard disk. An MPEG video decoder reads out this recoded data sequence in a reverse time-series manner and decodes it successively. Then the thus decoded data are converted to image video signals by a second display circuit, so as to be displayed on a display.

Claims

1. An image processing apparatus, comprising integrally:

a first block including;

a front-end decoder which decodes a first coded data sequence; and

a first display circuit which generates an image video signal from data decoded by the front-end decoder;

a second block including;

an image input circuit which converts the image video signal, outputted from said first block, to a video data sequence; and

an encoder which codes the video data sequence into a second coded data sequence; and

a third block including;

a back-end decoder which decodes the second coded data sequence outputted from said second block; and

a second display circuit which generates an image video signal from data decoded by the back-end decoder,

said first block, second block and third block being integrally mounted,

wherein, for at least one block of said first block, second block and third block, all components included in said at least one block are mounted as part of a single integrated circuit (IC) chip.

8. An image processing apparatus according to claim 1, wherein said first block and third block are video reproducing LSIs, and said second block is a video recording LSI.

14. An image processing apparatus according to claim 1, the first coded data sequence is coded in compliance with MPEG.

2. An image processing apparatus, comprising integrally:

a first integrated circuit (IC) chip including;

a front-end decoder which decodes a first coded data sequence; and

a first display circuit which generates an image video signal from data decoded by the front-end decoder;

a second IC chip including;

an image input circuit which converts the image video signal, outputted from said first IC chip, to a video data sequence; and

an encoder which codes the video data sequence into a second coded data sequence; and

a third IC chip including;

a back-end decoder which decodes the second coded data sequence outputted from said second IC chip; and

a second display circuit which generates an image video signal from data decoded by the back-end decoder,

said first IC chip, second IC chip and third IC chip being integrally mounted.

9. An image processing apparatus according to claim 2, wherein said first IC chip and third IC chip are video reproducing LSIs, and said second IC chip is a video recording LSI.

15. An image processing apparatus according to claim 2, the first coded data sequence is coded in compliance with MPEG.

3. An image processing apparatus, comprising integrally:

a first block including;

a front-end decoder which decodes a first coded data sequence; and

a first display circuit which generates an image video signal from data decoded by the front-end decoder;

a second block including;

an image input circuit which converts the image video signal, outputted from said first block, to a video data sequence; and

an encoder which codes the video data sequence into a second coded data sequence; and

a third block including;

a back-end decoder which decodes the second coded data sequence outputted from said second block; and

a second display circuit which generates an image video signal from data decoded by the back-end decoder,

said first block, second block and third block being integrally mounted,

wherein all components included in at least said second and third blocks are mounted as part of a single integrated circuit (IC) chip, and both recording and reproduction of image data are processed and controlled by said single IC chip.

10. An image processing apparatus according to claim 3, wherein said first block and third block are video reproducing LSIs, and said second block is a video recording LSI.

16. An image processing apparatus according to claim 3, the first coded data sequence is coded in compliance with MPEG.

4. An image processing apparatus, comprising integrally:

a first block including;

a front-end decoder which decodes a first coded data sequence; and

a first display circuit which generates an image video signal from data decoded by the front-end decoder;

a second block including;

an image input circuit which converts the image video signal, outputted from said first block, to a video data sequence; and

an encoder which codes the video data sequence into a second coded data sequence; and

a third block including;

a back-end decoder which decodes the second coded data sequence outputted from said second block; and

a second display circuit which generates an image video signal from data decoded by the back-end decoder,

said first block, second block and third block being integrally mounted,

wherein all components included in at least said first and second blocks are mounted as part of a single integrated circuit (IC) chip, and both recording and reproduction of image data are processed and controlled by said single IC chip.

11. An image processing apparatus according to claim 4, wherein said first block and third block are video reproducing LSIs, and said second block is a video recording LSI.

17. An image processing apparatus according to claim 4, the first coded data sequence is coded in compliance with MPEG.

5. An image processing apparatus, comprising integrally:

a first block including;

a front-end decoder which decodes a first coded data sequence; and

a first display circuit which generates an image video signal from data decoded by the front-end decoder;

a second block including;

an image input circuit which converts the image video signal, outputted from said first block, to a video data sequence; and

an encoder which codes the video data sequence into a second coded data sequence; and

a third block including;

a back-end decoder which decodes the second coded data sequence outputted from said second block; and

a second display circuit which generates an image video signal from data decoded by the back-end decoder,

said first block, second block and third block being integrally mounted,

wherein all components included in at least said first and third blocks are mounted as part of a single integrated circuit (IC) chip, and reproduction of image data in a plurality of channels is processed and controlled by the single IC chip.

12. An image processing apparatus according to claim 5, wherein said first block and third block are video reproducing LSIs, and said second block is a video recording LSI.

18. An image processing apparatus according to claim 5, the first coded data sequence is coded in compliance with MPEG.

6. An image processing apparatus, comprising integrally:

a decoder which decodes a first coded data sequence;

a display circuit which generates an image video signal from data decoded by said decoder;

an image input circuit which inputs the image video signal generated by said display circuit and converts the generated image video signal to a video data sequence; and

an encoder which codes the converted video data sequence into a second coded data sequence,

said decoder, display circuit, image input circuit and encoder being integrally mounted.

19. An image processing apparatus according to claim 6, the first coded data sequence is coded in compliance with MPEG.

7. An image processing apparatus, comprising integrally:

a first block including;

a front-end decoder which decodes a first coded data sequence in a time series manner; and

a first display circuit which generates a first image video signal from data decoded by the front-end decoder;

a second block including;

an image input circuit which converts the first image video signal, outputted from said first block, to a video data sequence; and

an encoder which codes the video data sequence into a second coded data sequence;

a third block including;

a back-end decoder which decodes the second coded data sequence outputted from said second block in a reverse time-series manner; and

a second display circuit which generates a second image video signal from data decoded by the back-end decoder; and

a switching circuit which switches an output of the first image video signal from said first block functioning as forward reproduction and an output of the second image video signal from said third block functioning as reverse reproduction,

said first block, second block, third block and switching circuit being integrally mounted,

wherein the first image video signal from said first block are also inputted to said second and third blocks while being outputted as forward reproduction via said switching circuit, so as to form a stand-by state in preparation for a switching to reverse reproduction.

13. An image processing apparatus according to claim 7, wherein said first block and third block are video reproducing LSIs, and said second block is a video recording LSI.

20. An image processing apparatus according to claim 7, the first coded data sequence is coded in compliance with MPEG.