Pattern recognition apparatus for detecting predetermined pattern contained in input signal

• US 20020181765A1
• Filed: 05/29/2002
• Published: 12/05/2002
• Est. Priority Date: 05/31/2001
• Status: Active Grant

• Current Assignee: Canon Kabushiki Kaisha (Canon Inc.)
• Original Assignee: Canon Kabushiki Kaisha (Canon Inc.)
• Inventors: Matsugu, Masakazu, Nomura, Osamu, Mori, Katsuhiko
• Granted Patent: US 7,039,233 B2
• Time in Patent Office: Days
• US Class Current: 382/158
• CPC Class Codes: G06V 10/454 Integrating the filters into a hierarchical structure, e.g. convolutional neural networks [CNN]
• CPC Class Codes: G06V 10/94 Hardware or software architectures specially adapted for image or video understanding

Abstract

A pattern recognition apparatus for detecting a predetermined pattern contained in an input signal is provided with plural detecting processing parts and 4A for detecting respectively different features for a same input, plural integrating processing parts for spatially integrating, for each process results, the features detected by the plural detecting processing parts, plural detecting memories for retaining the process results of the detecting processing parts, plural integrating memories for retaining the process results of the integrating processing parts, a global data line 1030 to which all the predetermined detecting processing parts and all the predetermined integrating memories are connected at a certain timing, and plural local data lines each of which is connected to a predetermined set of the detecting processing parts, the integrating processing parts and the detecting memory.

Claims

1. A pattern recognition apparatus for detecting a predetermined pattern contained in an input signal, comprising:

plural detecting processing means for detecting respectively different features for a same input;

plural integrating processing means for spatially integrating, for each process results, the features detected by said plural detecting processing means;

plural detecting memories for retaining the process results of said detecting processing means;

plural integrating memories for retaining the process results of said integrating processing means;

a common data line to which all said predetermined detecting processing means and all said predetermined integrating memories are connected at a certain timing; and

plural local data lines each of which is connected to a predetermined set of said detecting processing means, said integrating processing means and said detecting memory;

wherein, in entering the process results of said detecting processing means retained in said detecting memories into said integrating processing means, data of a same address in said plural detecting memories are read and entered into said integrating processing means; and

in entering the process results of said integrating processing means retained in said integrating memories into said detecting processing means, data of a same address in said plural detecting memories are read and entered into said detecting processing means.

2. A pattern recognition apparatus according to claim 1, wherein, in entering the process results of said integrating processing means into said integrating memories and/or in entering the data of said integrating memories into said detecting processing means, said integrating processing means and said integrating memories are so controlled as to use said common data line on time-shared basis.

3. A pattern recognition apparatus according to claim 1, wherein said common data line includes plural sub common data lines and plural switches;

each of said sub common data lines is connected one of said integrating memories;

in entering the process results of said plural integrating processing means into said integrating memories, said plural sub common data lines are utilized; and

in entering the process results of said integrating processing means, retained in said integrating memories, into said detecting processing means, said plural sub common data lines are connected by controlling said switches and used as an imaginary single data line.

4. A pattern recognition apparatus according to claim 1, wherein said common data line includes plural shared common data lines;

each of said shared common data lines is connected to one of said predetermined integrating memories and all said predetermined detecting processing means; and

in entering the process results of said plural integrating processing means into said plural integrating memories and/or in entering the process results of said integrating processing means, retained in said integrating memories, into said detecting processing means, said plural shared data lines are used.

5. A pattern recognition apparatus according to claim 1, further comprising:

configuration information memory means for storing configuration information; and

circuit configuration control means for reconstructing the circuit configuration of said detecting processing means and said integrating processing means, based on the configuration information of said configuration information memory means.

6. A pattern recognition apparatus according to claim 5, wherein said circuit configuration control means executes such control as not to simultaneously execute the reconstruction of the circuit configuration of said detecting processing means and the reconstruction of the circuit configuration of said integrating processing means.

7. A pattern recognition apparatus according to claim 1, further comprising an external interface connected to said common data line, wherein the results in said detecting memories and in said integrating memories are read out through said external interface as an interim result of the process.