Dynamically reconfigurable signal processing circuit, pattern recognition apparatus, and image processing apparatus
First Claim
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1. A signal processing circuit comprising:
- an arithmetic processing circuit;
circuit arrangement information storage means for storing circuit arrangement information; and
circuit arrangement control means for outputting a predetermined arrangement control signal to said arithmetic processing circuit on the basis of the circuit arrangement information read out from said circuit arrangement information storage means, wherein said arithmetic processing circuit executes a plurality of different signal processing functions by reconstructing a circuit on the basis of the predetermined arrangement control signal.
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Abstract
A plurality of signal processing functions are achieved with the same arithmetic processing circuit by controlling wiring arrangements or signal modulation in accordance with a predetermined arrangement control signal that is output based on circuit arrangement information read from a circuit arrangement information storage unit. Hierarchical parallel processing is realized with small-scale circuit configuration. Further, detection of a predetermined feature and integration of the detection results can be efficiently performed.
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Citations
71 Claims
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1. A signal processing circuit comprising:
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an arithmetic processing circuit;
circuit arrangement information storage means for storing circuit arrangement information; and
circuit arrangement control means for outputting a predetermined arrangement control signal to said arithmetic processing circuit on the basis of the circuit arrangement information read out from said circuit arrangement information storage means, wherein said arithmetic processing circuit executes a plurality of different signal processing functions by reconstructing a circuit on the basis of the predetermined arrangement control signal. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60)
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61. An image processing apparatus comprising:
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image input means; and
image processing means for time-serially executing a plurality of spatial filter arithmetic operations for single image data input from said image input means in correspondence with a plurality of different spatial filter characteristics. - View Dependent Claims (62, 63, 64, 65, 66, 67, 68, 69, 70, 71)
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Specification