Circuit simulation

• US 20020183990A1
• Filed: 01/11/2002
• Published: 12/05/2002
• Est. Priority Date: 01/11/2001
• Status: Active Grant

• Current Assignee: PC Krause & Associates, Inc.
• Original Assignee: PC Krause & Associates, Inc.
• Inventors: Jatskevich, Juri V., Wasynczuk, Oleg
• Granted Patent: US 7,353,157 B2
• Time in Patent Office: Days
• US Class Current: 703/2
• CPC Class Codes: G06F 30/367 Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods

Abstract

A system, method, and apparatus select state variables for, build state equations of, and simulate time-domain operation of an electronic circuit. The circuit is modeled with three branch types (inductor, resistor, voltage source in series; capacitor, resistor, current source in parallel; and switch), including four pre-defined switch types (unidirectional unlatched, bidirectional unlatched, unidirectional latched, and bidirectional latched). Automated analyses determine efficient state variables based on the currently active circuit topology, and state equations are built and applied. Switching logic determines when switch states change, and state equations for the new topology are either drawn from a cache (if the topology has already been processed) or derived anew. The switch control signals may be combined into a single switching variable, defined as a function of the state output.

Claims

1. A method, comprising:

creating one or more data structures sufficient to model an electronic circuit as a collection of n elements consisting of;

zero or more LRV elements, each having at least one of (a) a non-zero inductance parameter L_br, (b) a non-zero resistance parameter r_br, or (c) a non-zero voltage source parameter e_br, but neither a non-zero capacitance parameter, nor a non-zero current source parameter, nor a switch parameter;

zero or more CRI elements, each having at least one of (a) a non-zero capacitance parameter C_br, (b) a non-zero resistance parameter r_br, or (c) a non-zero current source parameter j_br, but neither a non-zero inductance parameter, nor a non-zero voltage source parameter, nor a switch parameter; and

zero or more switching elements, each having a switch state and neither a non-zero inductance parameter, a non-zero capacitance parameter, a non-zero resistance parameter, a non-zero voltage source parameter, nor a non-zero current source parameter; and

automatically generating a first set of state equations from said one or more data structures; and

simulating operation of the electronic circuit by application of said first set of state equations;

wherein n is at least two, and the collection comprises either

an LRV element for which at least two of L_br, r_br, or e_br are non-zero, or

a CRI element for which at least two of C_br, r_br, or j_br are non-zero.

2. The method of claim 1, wherein said simulating comprises producing state output, data, the method further comprising:

modifying the parameters in said first set of state equations as a function of said state output data.

3. The method of claim 1, further comprising:

modifying the parameters in said first set of state equations based on a time-varying parameter of at least one element in said collection.

4. The method of claim 1, further comprising:

generating a second set of state equations from said one or more data structures upon the occurrence of a first topology change event.

5. The method of claim 4, wherein said generating said second set of state equations comprises modifying only the subset of said first set of state equations that depend on the one or more switching elements that have changed.

6. The method of claim 4, wherein each unique vector of switch states represents a topology of the overall circuit, and further comprising:

storing said first set of state equations in a cache;

after a second topology change event, determining whether a set of state equations in the cache represents the new topology;

if said determining is answered in the affirmative, using the set of state equations that represents the new topology to simulate operation of the circuit after the second topology change event; and

if said determining is answered in the negative, building a third set of state equations that represents the new topology, and using the third set of state equations to simulate operation of the circuit after the second topology change event.

7. The method of claim 6, further comprising:

storing said second set of state equations in a cache;

after a third topology change event, deciding whether a set of state equations in the cache represents the new topology;

if said deciding is concluded in the affirmative, using the set of state equations from the cache that represents the new topology to simulate operation of the circuit after the third topology change event; and

if said deciding is concluded in the negative, building a new set of state equations that represents the new topology, and using the new set of state equations to simulate operation of the circuit after the third topology change event.

8. A method, comprising:

creating one or more data structures that together store characteristics of a plurality of active branches B^active that make up a graph of nodes and branches that form a circuit, wherein B^active consists of

a set B^L of zero or more inductive branches, each having a non-zero inductive component but neither a capacitive component nor a variable switch state;

a set B^C of zero or more capacitive branches, each having a non-zero capacitive component but neither an inductive component nor a variable switch state; and

a set B^A of additional branches, each having neither an inductive component, nor a capacitive component;

partitioning B^active into a first branch set B_tree^active and a second branch set B_link^active, where the branches in B_tree^active form a spanning tree over B^active, giving priority in said partitioning to branches not in B^L over branches in B^L;

sub-partitioning B_link^active into a third branch set B_link^L and a fourth branch set B_link^CA, where B_link^L=B_link^active∩

B^L;

identifying a fifth branch set B^CA as the union of

B_link^CA,

B^C∩

B_tree^active, and

those branches in B_tree^active that form a closed graph when combined with B_link^CA;

partitioning B^CA into a sixth branch set {tilde over (B)}_tree^CA and a seventh branch set {tilde over (B)}_link^CA, where the branches in {tilde over (B)}_tree^CA form a spanning tree over B^CA, giving priority in said partitioning to branches in B^C over branches not in B^C;

identifying an eighth branch set B_tree^C={tilde over (B)}_tree^CA∩

B^C;

selecting a set of state variables comprising;

for each branch of B_link^L, either the inductor current or inductor flux, and

for each branch of B_tree^C, either the capacitor voltage or capacitor charge; and

simulating a plurality of states of the circuit using the set of state variables.

9. The method of claim 8, wherein said partitioning steps each comprise an application of a weighted spanning tree algorithm.

10. The method of claim 9 wherein, for some positive numbers w_L and w_C:

for the partitioning of B^active, a minimum spanning tree algorithm is used

${\mathrm{\omega <br><br>}}_L<br><br>\left(b_j\right)=\{\begin{array}{c}{w}_L<br><br>\text{\hspace{1em}<br><br>}<br><br>\mathrm{if}<br><br>\text{\hspace{1em}<br><br>}<br><br>\mathrm{branch}<br><br>\text{\hspace{1em}<br><br>}<br><br>b_j\in <br><br>B^L\\ 0<br><br>\text{\hspace{1em}<br><br>}<br><br>\mathrm{otherwise}\end{array};<br><br>$

for the partitioning of B^CA, a maximum spanning tree algorithm is used

${\mathrm{\omega <br><br>}}_C<br><br>\left(b_j\right)=\{\begin{array}{c}{w}_C<br><br>\text{\hspace{1em}<br><br>}<br><br>\mathrm{if}<br><br>\text{\hspace{1em}<br><br>}<br><br>\mathrm{branch}<br><br>\text{\hspace{1em}<br><br>}<br><br>b_j\in <br><br>B^C\\ 0<br><br>\text{\hspace{1em}<br><br>}<br><br>\mathrm{otherwise}\end{array}.$

11. A system, comprising a processor and a computer-readable medium in communication with said processor, said medium containing programming instructions executable by said processor to:

build state equations for a first topology of an electronic circuit having at least two switching elements, wherein each switching element has a switching state;

solve said state equations at time t_i to provide a state output vector, in which at least two elements control the switching states of the switching elements;

calculate the value of a switching variable as a function of the state output vector, wherein the value reflects whether the switching state of at least one of the switching elements is changing; and

if the value of the switching variable at time t_i indicates that at least one of the switching elements is changing, determine a second topology of the electronic circuit for time t_i⁺ and obtain state equations for the second topology.

12. The system of claim 11, wherein:

said programming instructions comprise a state equation building module, a solver module for ordinary differential equations, and a switching logic module;

said building is performed by the state equation building module;

said solving and calculating are performed by the solver module; and

said determining is performed by the switching logic module.

13. The system of claim 12, wherein said obtaining is performed by said switching logic module.

14. The system of claim 12, wherein said obtaining is performed by said state equation building module.

15. The system of claim 12, wherein:

at a time t_j, at least two switching elements are each either rising-sensitive or falling-sensitive switches, wherein

rising-sensitive switches change switching state if and only if a controlling element of the state vector has passed from a negative value to a non-negative value; and

falling-sensitive switches change switching state if and only if a controlling element of the state vector has passed from a positive value to a non-positive value; and

the function is the arithmetic maximum of

a maximum of all elements of the state vector that control rising-sensitive switches, and

the negative of the minimum of all controlling elements of the state vector that control falling-sensitive switches.

16. A system for simulating electronic circuits, comprising a processor and a computer-readable medium in communication with said processor, said medium containing programming instructions executable by said processor to read element parameters and node connection information from a data stream comprising at least one switch type specification, the at least one switch type specification being selected from the group consisting of:

a unidirectional, unlatched switch;

a bidirectional, unlatched switch;

a unidirectional, latched switch; and

a bidirectional, latched switch; and

wherein said instructions are further executable by said processor automatically to calculate state equations for the circuit given the states of switches specified by said at least one switch type specification.