System and method for using native floating point microprocessor instructions to manipulate 16-bit floating point data representations

• US 20020184282A1
• Filed: 03/01/2001
• Published: 12/05/2002
• Est. Priority Date: 03/01/2001
• Status: Active Grant

• Current Assignee: Microsoft Technology Licensing LLC (Microsoft Corporation)
• Original Assignee: Microsoft Corporation
• Inventors: Stokes, Michael D., Blinn, James F., Yuval, Gideon A., Wilt, Nicholas P.
• Granted Patent: US 7,330,864 B2
• Time in Patent Office: Days
• US Class Current: 708/495
• CPC Class Codes: G06F 7/483 Computations with numbers represented by a non-linear combination of denominational numbers, e.g. rational numbers, logarithmic number system or floating-point numbers G06F7/4806, G06F7/4824, G06F7/49, G06F7/491, G06F7/544 take precedence
• CPC Class Codes: G06F 9/30025 Format conversion instructions, e.g. Floating-Point to Integer, decimal conversion
• CPC Class Codes: H03M 7/24 Conversion to or from floating-point codes

Abstract

A method for providing a 16-bit floating point data representation where the 16-bit floating point data representation may be operated upon by a microprocessors native floating point instruction set. The method contemplates the use a variety of techniques for converting the 16-bit floating point number into a representative native floating point value. Thereafter, the native microprocessor floating point instruction set may perform operations upon the converted data. Upon completion, the native floating point data representation may be converted back into the 16-bit floating point value.

Claims

1. A method for using a microprocessor'"'"'s native floating point instructions to manipulate 16-bit floating point data representations, comprising:

providing a 16-bit floating point data representation having a sign bit, an exponent and a significand;

converting the 16-bit floating point data representation into a floating point format native to the microprocessor;

performing an operation on the native floating point representation using at least one of the microprocessors floating point instructions; and

converting the native floating point data representation into a 16-bit floating point data representation.

2. The method as recited in claim 1 wherein the 16-bit data representation represents information for use in image processing.

3. The method as recited in claim 2 wherein the information comprises color information.

4. The method as recited in claim 3 wherein the color information comprises transparency information.

5. The method as recited in claim 2 wherein the information comprises texture image data.

6. The method as recited in claim 2 wherein the information comprises texture coordinates.

7. The method as recited in claim 2 wherein the information comprises displacement maps

8. The method as recited in claim 2 wherein the information comprises bump maps.

9. The method as recited in claim 2 wherein the information comprises vertex information that controls graphics hardware.

10. The method as recited in claim 9 wherein the vertex information comprises joint interpolation data.

11. The method as recited in claim 1 wherein the step of converting the native floating point representation to a 16-bit floating point value comprises rounding the native floating point value to a 16-bit floating point value.

12. The method as recited in claim 11 wherein the rounding comprises clamping values above the maximum representable 16-bit floating point value to infinity.

13. The method as recited in claim 11 wherein the rounding comprises clamping values below the minimum representable 16-bit floating point value to zero

14. The method as recited in claim 11 comprises rebiasing the 16-bit floating point exponent by subtracting a constant from the native floating point exponent.

15. The method as recited in claim 11 wherein the significand is rounded to nearest representable 16-bit floating point number.

16. The method as recited in claim 11 wherein the rounding is performed using SIMD instructions.

17. The method as recited in claim 16 wherein the SIMD instructions are selected from the set consisting of integer or floating point SIMD instructions.

18. The method as recited in claim 11 wherein the significand is rounded to the nearest even representable 16-bit floating point number.

19. The method as recited in claim 11 wherein the rounding is performed using integer instructions.

20. The method as recited in claim 11 wherein the rounding is performed using floating point instructions.

21. The method as recited in claim 1 wherein the 16-bit floating point data representation is biased by 2^e−

1−

1 whereby the exponent of zero lies proximate the middle of a range of exponent values.

22. The method as recited in claim 1 wherein the 16-bit floating point data representation has an exponent biased selected such that a range of values represented by the floating point number is between about zero and one.

23. The method as recited in claim 1 wherein the 16-bit floating point data representation definition such that an exponent value of 2^e−

1 represent NaN values.

24. The method as recited in claim 1 wherein the native floating point data representation is a 32-bit floating point data representation.

25. The method as recited in claim 1 wherein the step of converting the 16-bit floating point value to a native floating point representation to a comprises providing a lookup table having the conversion from 16-bit floating point to native floating point.

26. The method as recited in claim 25 wherein a lookup table is provided for converting the sign and exponent of the 16-bit floating point value into the native floating point sign and exponent.

27. The method as recited in claim 1 wherein the step of converting the native floating point representation to a 16-bit floating point value comprises scaling the significand by a predetermined scaling factor.

28. The method as recited in claim 1 wherein the step of converting the native floating point representation to a 16-bit floating point value comprises flushing 16-bit denormals are Flushed To Zero

29. The method of claim 1 wherein (16-bit) denormals are generated by converting a scaled float to an integer using rounded float-to-integer conversion instruction.

30. The method of claim 1, wherein (16-bit) denormals are generated by using addition of 3*2{circumflex over (0)}X (where X depends on the precise format) to cause all irrelevant bits to drop off the right end (but cause rounding), leaving the relevant bits at the bottom of the floating-point value ready to be used as an integer value.

31. The method of claim 1, where the logic for (16-bit) normals and denormals are both exercised, and a bit-mask is computed to select between them.

32. The method of claim 1, wherein denormal conversion is avoided when _all_the values in a region of memory convert to (16-bit) normals.

33. A computer-readable medium bearing computer-readable instructions for carrying out the steps recited in claim 1.

35. The method as recited in claim 34 wherein the 16-bit data representation represents information for use in image processing.

36. The method as recited in claim 35 wherein the information comprises color information.

37. The method as recited in claim 35 wherein the information comprises texture mapping information.

38. The method as recited in claim 36 wherein the color information comprises transparency information.

39. The method as recited in claim 35 wherein the information comprises texture image data.

40. The method as recited in claim 35 wherein the information comprises texture coordinates.

41. The method as recited in claim 35 wherein the information comprises displacement maps

42. The method as recited in claim 35 wherein the information comprises bump maps.

43. The method as recited in claim 35 wherein the information comprises vertex information that controls graphics hardware.

44. The method as recited in claim 43 wherein the vertex information comprises joint interpolation data.

45. The method as recited in claim 34 wherein the step of converting the native floating point representation to a 16-bit floating point value comprises rounding the native floating point value to a 16-bit floating point value.

46. The method as recited in claim 45 wherein the rounding comprises clamping values above the maximum representable 16-bit floating point value to infinity.

47. The method as recited in claim 45 wherein the rounding comprises clamping values below the minimum representable 16-bit floating point value to zero.

48. The method as recited in claim 45 comprises rebiasing the 16-bit floating point exponent by subtracting a constant from the native floating point exponent.

49. The method as recited in claim 45 wherein the significand is rounded to nearest representable 16-bit floating point number.

50. The method as recited in claim 45 wherein the significand is rounded to the nearest even representable 16-bit floating point number.

51. The method as recited in claim 45 wherein the rounding is performed using integer instructions.

52. The method as recited in claim 45 wherein the rounding is performed using floating point instructions.

53. The method as recited in claim 45 wherein the rounding is performed using SIMD instructions.

54. The method as recited in claim 53 wherein the SIMD instructions are selected from the set consisting of integer or floating point SIMD instructions.

55. The method as recited in claim 34 wherein the 16-bit floating point data representation is biased by 2^e−

1−

1 whereby the exponent of zero lies proximate the middle of a range of exponent values.

56. The method as recited in claim 34 wherein the 16-bit floating point data representation has an exponent biased selected such that a range of values represented by the floating point number is between about zero and one.

57. The method as recited in claim 34 wherein the 16-bit floating point data representation definition such that an exponent value of 2^e−

1 represent NaN values.

58. The method as recited in claim 34 wherein the native floating point data representation is a 32-bit floating point data representation.

59. A computer-readable medium bearing computer-readable instructions for carrying out the steps recited in claim 34.

34. A method for using a microprocessor'"'"'s native floating point instructions to manipulate 16-bit floating point data representations, comprising:

providing a 16-bit floating point data representation having a sign bit, an exponent and a significand;

converting the 16-bit floating point data representation into a floating point format native to the microprocessor; and

performing an operation on the native floating point representation using at least one of the microprocessors floating point instructions.

60. A method for using a native microprocessor floating-point instructions set, comprising:

providing information in a native floating point format;

providing a 16-bit floating point data representation having a sign bit, an exponent and a significand;

performing an operation on the information in the native floating point format; and

converting the information in the native bit floating point format into the 16-bit floating point format.

61. The method as recited in claim 60 wherein the 16-bit data representation represents information for use in image processing.

62. The method as recited in claim 61 wherein the information comprises color information.

63. The method as recited in claim 61 wherein the information comprises texture mapping information.

64. The method as recited in claim 62 wherein the color information comprises transparency information.

65. The method as recited in claim 61 wherein the information comprises texture image data.

66. The method as recited in claim 61 wherein the information comprises texture coordinates.

67. The method as recited in claim 61 wherein the information comprises displacement maps.

68. The method as recited in claim 61 wherein the information comprises bump maps.

69. The method as recited in claim 61 wherein the information comprises vertex information that controls graphics hardware.

70. The method as recited in claim 69 wherein the vertex information comprises joint interpolation data.

71. The method as recited in claim 60 wherein the 16-bit floating point data representation definition is such that an exponent value of 2^e−

1 represents NaN values.

72. The method as recited in claim 60 wherein the native floating point data representation is a 32-bit floating point data representation.

73. A computer-readable medium bearing computer-readable instructions for carrying out the steps recited in claim 60.

74. The method as recited in claim 60 wherein the conversion from 16-bit floating point to native floating point is performed by use of a lookup table.

75. The method as recited in claim 74 wherein the lookup table is indexed on a portion of the 16-bit floating point number.

76. The method as recited in claim 75 wherein the portion comprises the exponent.

77. The method as recited in claim 74 wherein the lookup table is used to determine whether the floating point value is a denormal value.

78. The method as recited in claim 60 wherein the conversion from 16-bit floating point to native floating point representation is performed using SIMD instructions.

80. The method as recited in claim 79 wherein the 16-bit data representation represents information for use in image processing.

81. The method as recited in claim 80 wherein the information comprises color information.

82. The method as recited in claim 81 wherein the color information comprises transparency information.

83. The method as recited in claim 80 wherein the information comprises texture image data.

84. The method as recited in claim 80 wherein the information comprises texture coordinates.

85. The method as recited in claim 80 wherein the information comprises displacement maps.

86. The method as recited in claim 80 wherein the information comprises bump maps.

87. The method as recited in claim 80 wherein the information comprises vertex information that controls graphics hardware.

88. The method as recited in claim 87 wherein the vertex information comprises joint interpolation data.

89. The method as recited in claim 79 wherein the 16-bit floating point data representation is biased by 2^e−

1−

1 whereby the exponent of zero lies proximate the middle of a range of exponent values.

90. The method as recited in claim 79 wherein the 16-bit floating point data representation has an exponent biased selected such that a range of values represented by the floating point number is between about zero and one.

91. The method as recited in claim 79 wherein the 16-bit floating point data representation definition such that an exponent value of 2^e−

1 represent NaN values.

92. The method as recited in claim 79 wherein the native floating point data representation is a 32-bit floating point data representation.

93. The method as recited in claim 79 wherein the step of converting the 16-bit floating point value to a native floating point representation comprises providing a lookup table having the conversion from 16-bit floating point to native floating point.

94. The method as recited in claim 93 wherein the lookup table is indexed on a portion of the 16-bit floating point number.

95. The method as recited in claim 94 wherein the portion comprises the exponent.

96. The method as recited in claim 94 wherein the lookup table is used to determine whether the floating point value is a denormal value.

97. The method as recited in claim 79 wherein the conversion from 16-bit floating point to native floating point representation is performed using SIMD instructions.

79. A method for using a microprocessor'"'"'s native floating point instructions to manipulate floating point data representations, comprising:

providing a 16-bit floating point data representation having a sign bit, an exponent and a significand;

performing an operation on the native floating point representation using at least one of the microprocessors floating point instructions;

converting the native floating point data representation into a 16-bit floating point data representation;

performing an operation on the 16-bit floating point data; and

converting the 16-bit floating point data representation into a floating point format native to the microprocessor.

98. A computer-readable medium bearing computer-readable instructions for carrying out the steps recited in claim 79.