Data bus system including posted reads and writes

• US 20020184453A1
• Filed: 06/29/2001
• Published: 12/05/2002
• Est. Priority Date: 06/05/2001
• Status: Abandoned Application

• Current Assignee: 3Com Corporation (HP Inc.)
• Original Assignee: 3Com Corporation (HP Inc.)
• Inventors: Jennings, Kevin, Creedon, Tadhg, Gavin, Vincent, Coburn, Derek, Lardner, Mike, De Paor, Denise, Hyland, Kevin J., Hughes, Suzanne M.
• Application Number:
  US09/893,658
• Publication Number:
  US 20020184453A1
• Time in Patent Office: Days
• US Class Current: 711/150
• CPC Class Codes: G06F 13/1605 based on arbitration arbitration in handling access to a common bus or bus system G06F13/36
• CPC Class Codes: G06F 13/4243 with synchronous protocol

Abstract

A data bus system in which a read or write transaction includes an identification of the initiator of the transaction and optionally an identification of the transaction as a number in a cyclic progression and optionally a request for an acknowledgement. The system allows confirmation that a particular transaction has occurred before a succeeding transaction is enabled to

Claims

1. An application specific integrated circuit comprising

a memory controller for storing and retrieving addressed data messages in memory,

a multiplicity of operational cores and at least one arbiter for controlling the order of passage of transactions through said arbiter, and

a memory bus, having a multiplicity of signal lines, for coupling transactions between each core and said memory controller by way of said at least one arbiter,

wherein said cores initiate writing transactions and reading transactions by means of which said data messages are stored in and retrieved from said memory by way of said memory bus and said arbiter,

wherein a writing transaction comprises placing on respective lines of said bus a write request and an identifier of a source of the writing transaction, and

wherein said writing transaction further comprises returning to said source an acknowledgement signal including said identifier.

2. A circuit according to claim 1 wherein said writing transaction includes placing on said bus an identifier of said writing transaction and said acknowledgement includes said identifier of said writing transaction.

3. A circuit according to claim 1 wherein a writing transaction includes a request signal indicating whether said acknowledgement is required.

4. A circuit according to claim 1 wherein a reading transaction comprises placing on respective lines of said bus a read request and an identifier of an initiator of the request and further comprises sending with the read data an acknowledgement including the identifier of the initiator.

5. An application specific integrated circuit comprising

a memory controller for storing and retrieving addressed data messages in memory,

a multiplicity of operational cores and at least one arbiter for controlling the order of passage of transactions through said arbiter,

a memory bus, having a multiplicity of signal lines, for coupling transactions between each core and said memory controller by way of said at least one arbiter, and

at least one data processor coupled by way of said bus and said arbiter to said memory controller

wherein said cores and said processor initiate writing transactions and reading transactions by means of which said data messages can be stored in said memory by way of said memory bus and said arbiter,

wherein a writing transaction comprises placing on respective lines of said bus a write request and identifiers of the source of the transaction and of the writing transaction, and

wherein said writing transaction further comprises returning to said source an acknowledgement signal including said identifiers.

6. A circuit according to claim 5 wherein a reading transaction comprises placing on respective lines of said bus a read request and identifiers of an initiator of the request and the read transaction and further comprises sending with the read data an acknowledgement including the identifiers of the initiator and the read transaction.

7. A circuit according to claim 5 and further comprising a register bus extending to and from said cores and said processor is coupled to provide register transactions on said register bus.

8. A circuit according to claim 7 and including a bridge coupled to a section of said memory bus and to said register bus and wherein said processor sends register transactions to and receives transaction from said bridge, which translates said register transactions between the memory bus and the register bus.

9. An application specific integrated circuit comprising

a memory controller for storing and retrieving addressed data messages in memory,

a multiplicity of operational cores,

a memory bus, having a multiplicity of signal lines, for coupling transactions between each core and said memory controller,

wherein said cores initiate writing transactions and reading transactions by means of which said data messages can be stored in and retrieved from said memory by way of said memory bus,

wherein each transaction comprises a request for the transaction, an identifier of the source of the transaction and an identifier of said transaction.

10. A circuit according to claim 9 wherein at least some transactions include a request for an acknowledgement and further include returning to said source an acknowledgement signal including the identifiers of the source and the writing transaction.

11. A circuit according to claim 9 wherein each identifier comprises a multibit field

12. A circuit according to claim 9 wherein each of said cores has a unique source identifier.

13. A circuit according to claim 9 wherein for each core the identifer of a transaction comprises a number in a respective cyclic sequence.

15. A circuit according to claim 14 wherein each identifier comprises a multibit field.

16. A circuit according to claim 14 wherein each of said cores has a unique source identifier.

17. A circuit according to claim 14 wherein for each core the identifier of a transaction comprises a number in a respective cyclic sequence.

14. An application specific integrated circuit comprising

a memory controller for storing and retrieving addressed data messages in memory, and

a memory bus, having a multiplicity of signal lines, for coupling transactions between each core and said memory controller, and wherein

(I) said cores initiate writing transactions and reading transactions by means of which said data messages can be stored in and retrieved from said memory by way of said memory bus,

(II) each transaction comprises a write request, an identifier of a source of the transaction and an identifier of the writing transaction,

(III) a writing transaction further comprises returning to said source an acknowledgement signal including said identifier, and

(IV) a reading transaction comprises a read request and identifiers of at least an initiator of the request and the respective reading transaction and further comprises an acknowledgement including the identifiers of the initiator and the respective read transaction.

18. An application specific integrated circuit comprising

(a) a memory controller for storing and retrieving addressed data messages in memory, and

(b) a memory bus, having a multiplicity of signal lines, for coupling transactions between each core and said memory controller, and wherein

(I) said cores initiate writing transactions and reading transactions by means of which said data messages can be stored in and retrieved from said memory by way of said memory bus,

(II) a writing transaction comprises a write request, an identifier of a source of the transaction and an identifier of the writing transaction,

(III) a writing transaction further comprises returning to said source an acknowledgement signal including said identifiers,

(IV) a reading transaction comprises a read request and identifiers of at least an initiator of the request and the respective reading transaction and further comprises an acknowledgement including the identifiers of the initiator and the respective read transaction.

(V) each identifier comprises a multibit field;

(VI) each of said cores has a unique source identifier, and

(VII) for each core the identifer of a transaction comprises a number in a respective cyclic sequence.