METHODS AND APPARATUS FOR COMBINING A PLURALITY OF MEMORY ACCESS TRANSACTIONS

• US 20020184460A1
• Filed: 06/04/1999
• Published: 12/05/2002
• Est. Priority Date: 06/04/1999
• Status: Active Grant

• Current Assignee: Oracle America, Inc. (Oracle Corporation)
• Original Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Inventors: KESKAR, SHRINATH, TREMBLAY, MARC
• Granted Patent: US 6,571,319 B2
• Time in Patent Office: Days
• US Class Current: 711/167
• CPC Class Codes: G06F 9/30043 LOAD or STORE instructions; Clear instruction
• CPC Class Codes: G06F 9/30181 Instruction operation extension or modification
• CPC Class Codes: G06F 9/3824 Operand accessing
• CPC Class Codes: G06F 9/3834 Maintaining memory consistency

Abstract

Instruction combining logic combines data from a plurality of write transactions before the data is written into main memory. In one embodiment, the instruction combining logic receives write transactions generated from store pair instructions, stores data from the write transactions in a buffer, and combines the data in the buffer. The combined data is subsequently written to memory in a single write transaction. The instruction combining logic may determine whether the data from the transactions are in the same cache line before combining them. A programmable timer may be used to measure the amount of time that has elapsed after the instruction combining logic receives the first write transaction. If the elapsed time exceeds a predetermined limit before another write instruction is received, the instruction combining logic combines the data in the buffer and writes it to memory in a single write transaction.

Claims

1. A method comprising the steps of:

receiving a first instruction to write a first data word at a first address of memory;

receiving a second instruction to write a second data word at a second address of memory;

determining whether the first address and the second address are in the same cache line; and

generating a combined instruction to write the first and second data words in the first and second addresses of memory, respectively, if the first address and the second address are determined to be in the same cache line.

2. The method of claim 1, wherein the first and second data words are 8 bytes in length.

3. The method of claim 1, wherein the cache line is 32 bytes in length.

4. A method comprising the steps of:

receiving a first instruction to access a first data word at a first address of memory;

receiving a second instruction to access a second data word at a second address of memory;

determining whether the first address and the second address are in the same cache line; and

generating a combined instruction to access the first and second data words in the first and second addresses of memory, respectively, if the first address and the second address are determined to be in the same cache line.

5. The method of claim 4, wherein the first and second data words are 8 bytes in length.

6. The method of claim 4, wherein the cache line is 32 bytes in length.

7. A method comprising the steps of:

(a) receiving a first instruction to write a first data word at a first address of main memory;

(b) storing the first data word in a buffer;

(c) receiving a subsequent instruction to write a data word at an address of main memory;

(d) determining whether the first address and the address associated with the subsequent instruction are for the same cache line;

(e) storing the data word associated with the subsequent instruction in the buffer if the first address and the address associated with the subsequent instruction are determined to be for the same cache line;

(f) determining whether the data words stored in the buffer represents a full cache line;

(g) if the data words stored in the buffer is determined to not represent a full cache line, returning to step (c);

(h) if the data words stored in the buffer is determined to represent a full cache line, generating a combined instruction to write the data words stored in the buffer to main memory.

8. The method of claim 7, wherein the first data word and the data word associated with each subsequent instruction are 8 bytes in length.

9. The method of claim 7, wherein the cache line is 32 bytes in length.

10. A method comprising the steps of:

receiving a first instruction to write a first data word at a first address of memory;

initiating a timer after the first instruction is received;

if a preset amount of time has elapsed on the timer before a second instruction is received, executing the first instruction; and

if a preset amount of time has not elapsed on the timer before a second instruction is received, performing the steps of;

receiving a second instruction to write a second data word at a second address of memory;

determining whether the first address and the second address are in the same cache line; and

generating a combined instruction to write the first and second data words in the first and second addresses of memory, respectively, if the first address and the second address are determined to be in the same cache line.

11. A method comprising the steps of:

receiving a first instruction to write a first data word at a first address of memory;

receiving a second instruction;

determining whether the second instruction is for writing a second data word at a second address of memory;

if the second instruction is determined not to be for writing a second data word at a second address of memory, executing the first and second instructions;

if the second instruction is determined to be for writing a second data word at a second address of memory, performing the steps of;

determining whether the first address and the second address are in the same cache line; and

generating a combined instruction to write the first and second data words in the first and second addresses of memory, respectively, if the first address and the second address are determined to be in the same cache line.

12. An apparatus comprising:

means for identifying whether received instructions are write instructions;

a buffer;

means for storing portions of instructions determined to be write instructions in the buffer; and

means for generating a combined write instruction based upon the portions of instructions stored in the buffer.

13. An apparatus comprising:

means for receiving a first instruction to write a first data word at a first address of memory;

means for receiving a second instruction to write a second data word at a second address of memory;

means for determining whether the first address and the second address are in the same cache line; and

means for generating a combined instruction to write the first and second data words in the first and second addresses of memory, respectively, if the first address and the second address are determined to be in the same cache line.