Power loss memory back-up
First Claim
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1. A method comprising:
- detecting a reset condition;
verifying a memory controller is initialized; and
placing a memory system into a retention state.
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Abstract
A memory system provides one or more control signals for configuring and controlling a memory sub-system during a power failure or system reset. A power delay circuit and a power fail controller cooperate to quickly place the memory system in a retention state in the event a power failure event is detected. The power delay circuit detects either a reset signal or power failure to initiate the memory retention state. The power delay circuit and power fail controller ensure the memory system is initialized prior to entering the retention state.
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Citations
16 Claims
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1. A method comprising:
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detecting a reset condition;
verifying a memory controller is initialized; and
placing a memory system into a retention state. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A memory system comprising:
a power delay circuit external to a memory controller, wherein the power delay circuit instructs the memory system to run a retention routine during a power failure or reset condition. - View Dependent Claims (8, 9, 10, 11, 12, 14, 15, 16)
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13. A method placing a memory system in a data retention mode comprising:
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detecting either a power failure or reset signal;
generating a delay signal based on the reset signal; and
initiating a data retention routine if the delay signal indicates the memory system is initialized.
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Specification