Power loss memory back-up

• US 20020184574A1
• Filed: 05/31/2001
• Published: 12/05/2002
• Est. Priority Date: 05/31/2001
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Luckett, Richard P., Mackey, Richard P., Bissessur, Sailesh, Warren, James D.
• Granted Patent: US 7,000,146 B2
• Time in Patent Office: Days
• US Class Current: 714/47
• CPC Class Codes: G06F 1/24 Resetting means
• CPC Class Codes: G06F 1/30 Means for acting in the event of power-supply failure or interruption, e.g. power-supply fluctuations for resetting only G06F1/24

Abstract

A memory system provides one or more control signals for configuring and controlling a memory sub-system during a power failure or system reset. A power delay circuit and a power fail controller cooperate to quickly place the memory system in a retention state in the event a power failure event is detected. The power delay circuit detects either a reset signal or power failure to initiate the memory retention state. The power delay circuit and power fail controller ensure the memory system is initialized prior to entering the retention state.

Claims

1. A method comprising:

detecting a reset condition;

verifying a memory controller is initialized; and

placing a memory system into a retention state.

2. The method of claim 1, further comprising verifying the memory controller is initialized by delaying a reset signal.

3. The method of claim 1, further comprising monitoring the voltage level of a system to determine a power failure.

4. The method of claim 3, further comprising generating a reset condition when either a power failure or a reset request occurs.

5. The method of claim 4, further comprising verifying the reset request does not occur prior to initialization.

6. The method of claim 1, further comprising detecting the reset condition and verifying the memory controller is initialized external to the memory controller.

7. A memory system comprising:

a power delay circuit external to a memory controller, wherein the power delay circuit instructs the memory system to run a retention routine during a power failure or reset condition.

8. The memory system of claim 7, further comprising a power fail controller which prevents the retention routine from executing when the memory system is not configured.

9. The memory system of claim 7, wherein the power delay circuit outputs a reset signal is either a power failure or a system reset signal is detected.

10. The memory system of claim 9, wherein the power delay circuit outputs a delay signal when the output reset signal is caused by a system reset signal.

11. The memory system of claim 7, wherein the power delay circuit monitors a voltage detector to detect a power failure.

12. The memory system of claim 8, wherein the power fail controller may be internal to the memory controller.

14. The method of claim 13 further comprising monitoring the voltage level of a system to determine a power failure.

15. The method of claim 13, further comprising generating two output signals to the memory controller based on the delay signal.

16. The method of claim 13, further comprising preventing initiating the data retention routine if the reset signal is not de-asserted for a predetermined period of time.

13. A method placing a memory system in a data retention mode comprising:

detecting either a power failure or reset signal;

generating a delay signal based on the reset signal; and

initiating a data retention routine if the delay signal indicates the memory system is initialized.