Method and structure for buried circuits and devices

• US 20020185684A1
• Filed: 06/12/2001
• Published: 12/12/2002
• Est. Priority Date: 06/12/2001
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Campbell, John E., Srikrishnan, Kris V., Devine, William T.
• Granted Patent: US 6,759,282 B2
• Time in Patent Office: Days
• US Class Current: 257/347
• CPC Class Codes: H01L 21/743 Making of internal connections, substrate contacts
• CPC Class Codes: H01L 21/76251 using bonding techniques
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/11803 using field effect technology
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/66772 Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates H01L29/66666 takes precedence; thin film FinFETs H01L29/66795
• CPC Class Codes: H01L 29/78606 with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device H01L29/78642, H01L29/78645 take precedence
• CPC Class Codes: H01L 29/78612 for preventing the kink- or the snapback effect, e.g. discharging the minority carriers of the channel region for preventing bipolar effect
• CPC Class Codes: H01L 29/78648 arranged on opposing sides of the channel
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H10B 12/05 Making the transistor
• CPC Class Codes: H10B 12/373 the capacitor extending under or around the transistor

Abstract

A method and structure for fabricating an electronic device using an SOI technique that results in formation of a buried oxide layer. The method includes fabricating at least one first component of the electronic device and fabricating at least one second component of the electronic device, wherein the first component and the second component are on opposite sides of the buried oxide layer, thereby causing the buried oxide layer to perform a function within the electronic device. Entire circuits can be designed around this technique.

Claims

1. A method of fabricating an electronic device using an SOI technique, said SOI technique resulting in formation of a buried oxide layer, said method comprising:

fabricating at least one first component of said electronic device; and

fabricating at least one second component of said electronic device, wherein said at least one first component and said at least one second component are on opposite sides of said buried oxide layer, thereby causing said buried oxide layer to perform a function within said electronic device.

2. The method of claim 1, wherein said buried oxide layer is modified in order to enable said buried oxide layer to perform selected functions within said electronic device.

3. The method of claim 2 , wherein one of said components comprises a buried gate and said oxide layer is made thinner locally over said buried gate.

4. The method of claim 2, wherein one of said components is a body contact for an overlying gate and said oxide layer is not formed over said component.

5. The method of claim 1, wherein one of said components comprises a component embedded in a substrate beneath said buried oxide layer and said fabricating further comprising:

forming a trench in said substrate;

forming an insulator on at least one of a sidewall surface and a bottom surface; and

forming a conductor within said trench such that said conductor and a top surface of said substrate are essentially planar.

6. The method according to claim 1, wherein said at least one first component is initially fabricated on a first wafer and said at least one second component is initially fabricated on a second wafer, and said SOI fabrication comprises bonding said first wafer and said second wafer to form said buried oxide layer.

7. The method according to claim 1, wherein said buried oxide layer is formed by implanting oxygen.

8. A device fabricated according to claim 1.

9. A method of fabricating an electronic circuit using an SOI technique, said SOI technique resulting in formation of at least one buried oxide layer, said electronic circuit comprising a plurality of interconnected electronic devices, each said electronic device comprising a respective plurality of components, said method comprising:

fabricating a predetermined first set of said respective plurality of components to be on a first side of said at least one buried oxide layer; and

fabricating a predetermined second set of said respective plurality of components to be on a second side of said at least one buried oxide layer, said second side being the opposite side of said first side, wherein said buried oxide layer performs a function integral to the functioning of at least one of said electronic devices.

10. The method according to claim 9, wherein at least one of said respective plurality of components of a first device is also a component of a second device, thereby causing said first device and said second device to be interconnected without requiring an interconnection conductor.

11. An electronic circuit on a chip, said electronic circuit fabricated according to the method of claim 9.

13. The method of claim 12, wherein said fabrication provides a plurality of devices and at least one said device shares a device component with at least one other device, thereby electronically interconnecting said at least two devices without requiring a separate interconnecting conductor.

14. The method of claim 12, further comprising:

interconnecting at least one component in said first set of components with at least one component in said second set of components with a via penetrating said buried oxide layer.

16. The method of fabricating a DRAM cell array according to claim 15, further comprising:

forming a gate for each said FET, wherein said gate is formed on top of said buried oxide layer for a first set of DRAM cells in said array and said gate is formed beneath said buried oxide layer for a second set of DRAM cells.

17. The method of claim 15, wherein said buried capacitor comprises a buried conductive material encased by an insulation layer separating said conductive material from said substrate, said method further comprises:

forming an insulation layer in a trench in said substrate to be beneath said buried oxide layer; and

filling a region formed by said insulation layer with a conductive material.

19. The method of claim 18, wherein said capacitor insulator comprises at least a portion of said buried oxide layer.

20. The method of claim 18, wherein said capacitor insulator comprises an insulation material different from said buried oxide layer.

21. The method of claim 18, further comprising:

Forming an area of insulator material and a capacitor electrode above a device layer, overlying the BOX layer, part of said area located above said buried capacitor, and a conducting link in the device layer electrically connecting the respective charge plate regions of the buried and overlying capacitors, thereby increasing the value of capacitor in said DRAM cell.

22. A DRAM cell having a structure in accordance with claim 15.

23. A DRAM cell having a structure in accordance with claim 18.

25. An electronic chip fabricated using the method of claim 24.

27. An electronic chip containing a dynamic two-phase shift register fabricated according to the method of claim 26.

29. An electronic chip containing a CMOS circuit fabricated according to the method of claim 28.

30. The method of claim 28, further comprising:

forming below said device layer an interconnective conductor to interconnect at least two of said FETs.

31. The method of claim 30, wherein said interconnective conductor below said device layer is at least partially enclosed by said buried oxide layer.

32. The method of claim 28, wherein said CMOS circuit comprises at least one of the following:

at least one NOR circuit; and

at least one NAND circuit.

12. A method of SOI fabrication wherein a buried oxide layer is formed, said method comprising:

forming a first set of device components to be on a first side of said buried oxide layer; and

forming a second set of device components to be on a side opposite said first side, wherein said buried oxide layer performs a function integral to the functioning of at least one device comprised of components from said first set of components and components from said second set of components.

15. A method of fabricating a DRAM cell using an an SOI technique on a substrate, said SOI technique resulting in formation of at least one buried oxide layer, said method comprising:

forming a buried capacitor beneath said buried oxide layer;

subsequently, forming an FET source region and drain region on top of said buried oxide layer; and

interconnecting said capacitor to one of said source region or drain region with a via penetrating said buried oxide layer, said via comprised of a conductive material.

18. A method of fabricating a DRAM cell using an SOI technique, said SOI technique resulting in formation of at least one buried oxide (BOX) layer, whereby a capacitor for said DRAM cell is formed by a process comprising:

forming a buried electrode in a substrate, wherein said buried electrode serves as a lower capacitor charge plate; and

forming a diffusion link between the diffusion region of a transistor located on a upper side of said BOX and a region to comprise an upper charge plate of said capacitor, whereby said upper charged plate of said capacitor is formed on an upper side of said BOX when impressing a bias voltage on said buried electrode.

24. A method of fabricating an electronic circuit having a plurality of electronic devices using an SOI technique, said SOI technique resulting in formation of at least one buried oxide layer, said method comprising:

forming an interconnector of conductive material to interconnect at least two of said plurality of electronic devices, said interconnector at least partially enclosed by said buried oxide.

26. A method of fabricating a dynamic two-phase shift register, said method comprising:

forming a buried oxide layer using an SOI technique;

forming a plurality of FET transistors to be in a device layer above said buried oxide layer;

forming a first clock signal conductor on top of said device layer; and

forming a second clock signal conductor below said device layer, said second clock signal conductor at least partially enclosed by said buried layer.

28. A method of fabricating a CMOS circuit, said method comprising:

forming a buried oxide layer using an SOI technique; and

forming a plurality of FET transistors to be in a device layer above said buried oxide layer, wherein at least two of said FET transistors share a common diffusion region, thereby electrically interconnecting said at least two FET transistors without using a separate interconnecting conductive material.

33. A method of fabricating a FET using an SOI technique, said SOI technique resulting in formation of at least one buried oxide layer, said method comprising:

forming a first gate beneath said buried oxide layer; and

forming a second gate on top of said buried oxide layer.

34. An FET fabricated by the method of claim 33.

37. The electronic device of claim 35 , wherein said device is formed in a substrate beneath said buried oxide layer.

39. The electronic circuit of claim 38, wherein at least one of said interconnected devices is formed in a substrate beneath said buried oxide layer.

35. An electronic device comprising at least one SOI buried oxide layer, wherein said at least one buried oxide layer performs a function integral to said device.

36. An electronic device comprising at least one SOI buried oxide layer, wherein said at least one SOI buried oxide layer comprises a structural element integral to said device.

38. An electronic circuit comprising a plurality of interconnected devices, said circuit mounted on a wafer having at least one SOI buried oxide layer, wherein said at least one SOI buried oxide layer comprises a functional element integral to at least one of said devices.

40. An electronic circuit comprising a plurality of interconnected devices, said devices formed on a wafer having at least one SOI buried oxide layer, wherein said at least one SOI buried oxide layer comprises a structural element integral to at least one of said devices.

41. An electronic circuit comprising a plurality of interconnected devices, said devices formed on a wafer having at least one SOI buried oxide layer, wherein said at least two adjacent devices in said circuit share at least one device component, thereby electrically interconnecting said two devices without an interconnecting conductor, and wherein said at least one SOI buried oxide layer serves to isolate components of said two interconnected devices other than said shared at least one component.