Programmable resolution CMOS image sensor

• US 20020186312A1
• Filed: 11/27/2001
• Published: 12/12/2002
• Est. Priority Date: 11/27/2000
• Status: Abandoned Application

• Current Assignee: Vision-Sciences Incorporated (2941881 Canada, Inc.)
• Original Assignee: Vision-Sciences Incorporated (2941881 Canada, Inc.)
• Inventors: Stark, Moshe
• Application Number:
  US09/993,917
• Publication Number:
  US 20020186312A1
• Time in Patent Office: Days
• US Class Current: 348/302
• CPC Class Codes: H04N 25/44 by partially reading an SSIS array
• CPC Class Codes: H04N 25/46 by combining or binning pixels
• CPC Class Codes: H04N 25/78 Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters

Abstract

An image sensor includes a plurality of unit cells, each adapted to generate charge in response to photons incident thereon and array elements adapted to sum charge from one or more unit cells at a focal plane of the image sensor. Alternatively, the array elements may be adapted to change a resolution of the output of the image sensor at its focal plane. The invention includes the method performed by the image sensor.

Claims

1. An image sensor comprising:

a plurality of unit cells, each adapted to generate charge in response to photons incident thereon; and

array elements adapted to sum charge from one or more unit cells at a focal plane of said image sensor.

2. An image sensor according to claim 1 and wherein said array elements comprise:

charge transfer transistors, one per unit cell, adapted to transfer charge from their associated unit cells when activated;

a line decoder adapted to activate charge transfer transistors of one or more lines of unit cells; and

a column selector adapted to activate one or more columns of unit cells and to combine the charge transferred by activated charge transfer transistors of said activated columns.

3. An image sensor according to claim 2 and wherein said array elements comprise adjacent line means adapted to indicate to said line decoder to activate at least two adjacent lines and to said column selector to select one column thereby to combine charge from the corresponding unit cells in adjacent lines.

4. An image sensor according to claim 2 and wherein said array elements comprise adjacent column means adapted to indicate to said line decoder to activate one line and to said column selector to combine charge of at least two columns thereby to combine charge from at least two unit cells in adjacent columns.

5. An image sensor according to claim 2 and wherein said array elements comprise block means adapted to indicate to said line decoder to activate U adjacent lines and to said column selector to combine charge of V columns thereby to combine charge from U×

V unit cells in a U×

V block.

6. An image sensor according to claim 3 and comprising interlace means adapted to produce video output from said image sensor in an interlace mode.

7. An image sensor according to claim 6 and wherein said interlace means comprises means adapted to activate said adjacent line means to combine charge of pairs of unit cells in adjacent lines beginning with the odd lines adapted to an odd field output and of adjacent lines beginning with the even lines adapted to an even field output.

8. An image sensor according to claim 4 and comprising intercolumn means adapted to produce video output from said image sensor in an intercolumn mode.

9. An image sensor according to claim 8 and wherein said intercolumn means comprises means adapted to activate said adjacent column means to combine charge of pairs of adjacent columns beginning with the odd columns adapted to an odd field output and of adjacent columns beginning with the even columns adapted to an even field output.

10. An image sensor according to claim 5 and comprising block interlace means adapted to produce video output from said image sensor in a block interlace mode.

11. An image sensor according to claim 10 and wherein said block interlace means comprises means adapted to activate said block means to combine charge of 2×

2 blocks wherein the blocks of an odd field output begin with the block whose upper left-hand unit cell is in the first column, first line and wherein the blocks of an even field output begin with the block whose upper left-hand unit cell is in the second column, second line.

13. An image sensor according to claim 12 and wherein said array elements comprise:

charge transfer transistors, one per unit cell, adapted to transfer charge from their associated unit cells when activated;

a line decoder adapted to activate charge transfer transistors of one or more lines of unit cells; and

a column selector adapted to activate one or more columns of unit cells and to combine the charge transferred by activated charge transfer transistors of said activated columns.

14. An image sensor according to claim 13 and wherein said array elements comprise adjacent line means adapted to indicate to said line decoder to activate at least two adjacent lines and to said column selector to select one column thereby to combine charge from the corresponding unit cells in adjacent lines.

15. An image sensor according to claim 13 and wherein said array elements comprise adjacent column means adapted to indicate to said line decoder to activate one line and to said column selector to combine charge of at least two columns thereby to combine charge from at least two unit cells in adjacent columns.

16. An image sensor according to claim 13 and wherein said array elements comprise block means adapted to indicate to said line decoder to activate U adjacent lines and to said column selector to combine charge of V columns thereby to combine charge from U×

V unit cells in a U×

V block.

17. An image sensor according to claim 14 and comprising interlace means adapted to produce video output from said image sensor in an interlace mode.

18. An image sensor according to claim 17 and wherein said interlace means comprises means adapted to activate said adjacent line means to combine charge of pairs of unit cells in adjacent fines beginning with the odd lines adapted to an odd field output and of adjacent lines beginning with the even lines adapted to an even field output.

19. An image sensor according to claim 13 and comprising intercolumn means adapted to produce video output from said image sensor in an intercolumn mode.

20. An image sensor according to claim 19 and wherein said intercolumn means comprises means adapted to activate said adjacent column means to combine charge of pairs of adjacent columns beginning with the odd columns adapted to an odd field output and of adjacent columns beginning with the even columns adapted to an even field output.

21. An image sensor according to claim 13 and comprising block interlace means adapted to produce video output from said image sensor in a block interlace mode.

22. An image sensor according to claim 21 and wherein said block interlace means comprises means adapted to activate said block means to combine charge of 2×

2 blocks wherein the blocks of an odd field output begin with the block whose upper left-hand unit cell is in the first column, first line and wherein the blocks of an even field output begin with the block whose upper left-hand unit cell is in the second column, second line.

24. A method according to claim 23 and wherein said summing comprises:

activating charge transfer transistors of one or more lines of unit cells;

activating one or more columns of unit cells; and

combining the charge transferred by activated charge transfer transistors of said activated columns.

25. A method according to claim 23 wherein said summing comprises activating at least two adjacent lines and selecting one column thereby to combine charge from the corresponding unit cells in adjacent lines.

26. A method according to claim 23 and wherein said summing comprises activating one line and combining charge of at least two columns thereby to combine charge from at least two unit cells in adjacent columns.

27. A method according to claim 23 and wherein said summing comprises activating U adjacent lines and combining charge of V columns thereby to combine charge from U×

V unit cells in a U×

V block.

28. A method according to claim 25 and comprising producing video output from said image sensor in an interlace mode.

29. A method according to claim 28 and wherein said producing comprises combining charge of pairs of unit cells in adjacent lines beginning with the odd lines for an odd field output and of adjacent lines beginning with the even lines for an even field output.

30. A method according to claim 26 and comprising producing video output from said image sensor in an intercolumn mode.

31. A method according to claim 30 and wherein said producing comprises combining charge of pairs of adjacent columns beginning with the odd columns for an odd field output and of adjacent columns beginning with the even columns for an even field output.

32. A method according to claim 31 and comprising producing video output from said image sensor in a block interlace mode.

33. A method according to claim 32 and wherein said producing comprises combining charge of 2×

2 blocks wherein the blocks of an odd field output begin with the block whose upper left-hand unit cell is in the first column, first line and wherein the blocks of an even field output begin with the block whose upper left-hand unit cell is in the second column, second line.

35. A method according to claim 34 and wherein said changing comprises:

activating charge transfer transistors of one or more lines of unit cells;

activating one or more columns of unit cells; and

combining the charge transferred by activated charge transfer transistors of said activated columns.

36. A method according to claim 34 wherein said changing comprises activating at least two adjacent lines and selecting one column thereby to combine charge from the corresponding unit cells in adjacent lines.

37. A method according to claim 34 and wherein said changing comprises activating one line and combining charge of at least two columns thereby to combine charge from at least two unit cells in adjacent columns.

38. A method according to claim 34 and wherein said changing comprises activating U adjacent lines and combining charge of V columns thereby to combine charge from U×

V unit cells in a U×

V block.

39. A method according to claim 36 and comprising producing video output from said image sensor in an interlace mode.

40. A method according to claim 39 and wherein said producing comprises combining charge of pairs of unit cells in adjacent lines beginning with the odd lines for an odd field output and of adjacent lines beginning with the even lines for an even field output.

41. A method according to claim 37 and comprising producing video output from said image sensor in an intercolumn mode.

42. A method according to claim 41 and wherein said producing comprises combining charge of pairs of adjacent columns beginning with the odd columns for an odd field output and of adjacent columns beginning with the even columns for an even field output.

43. A method according to claim 42 and comprising producing video output from said image sensor in a block interlace mode.

44. A method according to claim 43 and wherein said producing comprises combining charge of 2×

2 blocks wherein the blocks of an odd field output begin with the block whose upper left-hand unit cell is in the first column, first line and wherein the blocks of an even field output begin with the block whose upper left-hand unit cell is in the second column, second line.

12. An image sensor comprising:

a plurality of unit cells, each adapted to generate charge in response to photons incident thereon; and

array elements adapted to change a resolution of the output of said image sensor at a focal plane of said image sensor.

23. A method comprising:

generating charge in response to photons incident on a plurality of unit cells of an image sensor; and

summing charge from one or more of said unit cells at a focal plane of said image sensor.

34. A method comprising:

generating charge in response to photons incident on a plurality of unit cells of an image sensor; and

changing a resolution of the output of said image sensor at a focal plane of said image sensor.