Method and circuitry for processing data

• US 20020186775A1
• Filed: 06/11/2002
• Published: 12/12/2002
• Est. Priority Date: 06/11/2001
• Status: Active Grant

• Current Assignee: STMicroelectronics Limited (STMicroelectronics NV)
• Original Assignee: STMicroelectronics Limited (STMicroelectronics NV)
• Inventors: Cordero, Rodrigo, Woodward, Patrice
• Granted Patent: US 7,839,937 B2
• Time in Patent Office: Days
• US Class Current: 375/240.26
• CPC Class Codes: H04N 21/426 Internal components of the client ; Characteristics thereof H04N5/44 takes precedence
• CPC Class Codes: H04N 21/42615 involving specific demultiplexing arrangements
• CPC Class Codes: H04N 21/434 Disassembling of a multiplex stream, e.g. demultiplexing audio and video streams, extraction of additional data from a video stream; Remultiplexing of multiplex streams; Extraction or processing of SI; Disassembling of packetised elementary stream demultiplexing of data packets for data networks, e.g. RTP/UDP H04L65/00
• CPC Class Codes: H04N 21/4341 Demultiplexing of audio and video streams
• CPC Class Codes: H04N 21/4345 Extraction or processing of SI, e.g. extracting service information from an MPEG stream

Abstract

The invention relates to circuitry for processing data. The circuitry comprises a plurality of filters arranged in parallel and means for storing input data. The input data is applied to the plurality of filters to provide at least two parallel results and means for carrying out an operation with respect to the results.

Claims

1. Circuitry for processing data, said circuitry comprising:

a plurality of filters arranged in parallel;

means for storing input data, said input data being applied to said plurality of filters to provide at least two parallel results; and

means for carrying out an operation with respect to said results.

2. Circuitry for processing data as claimed in claim 1, wherein at least one of said plurality of filters has associated therewith a mask.

3. Circuitry for processing data as claimed in claim 1, wherein said plurality of filters are provided in a conditional access memory arrangement.

4. Circuitry for processing data as claimed in claim 3, wherein said CAM arrangement comprises a separate CAM for each of said parallel results.

5. Circuitry for processing data as claimed in claim 1, wherein said means for carrying out an operation performs at least one logic operation.

6. Circuitry for processing data as claimed in claim 5, wherein said at least one logic operation is a Boolean operation.

7. Circuitry For processing data as claimed in claim 1, wherein said means for carrying out an operation provides a single result.

8. Circuitry for processing data as claimed in claim 1, wherein mask means are provided for applying a mask to at least one of said at least two parallel results.

9. Circuitry for processing data as claimed in claim 1 wherein said means for carrying out an operation are arranged to carry out said operation with respect of said parallel results in their entirety.

10. Circuitry for processing data as claimed in claim 1, wherein said means for carrying out an operation are arranged to carry out said operation with respect to only one or more of each of said parallel results.

11. Circuitry as claimed in claim 1, wherein said data comprises MPEG data.

12. Circuitry as claimed in claim 11, wherein said data comprises sections of MPEG data.

13. Circuitry as claimed in claim 12, wherein said data comprises headers of sections of MPEG data.

14. Circuitry as claimed in claim 1, wherein said circuitry is provided on an integrated circuit.

15. A method for processing data comprising:

applying input data to a plurality of filters in parallel to provide at least two parallel results;

carrying out an operation with respect to said results.