Data carrier comprising memory means for storing information significant for intermediate operating states
First Claim
1. A data carrier (2) comprising communication means (50) for communication with at least one communication station (1) in accordance with a communication sequence executed during the communication, the communication sequence comprising several communication steps, and in the data carrier (2) an intermediate operating state occurs as a result of a communication step of specific communication steps, and in the data carrier (2) intermediate operating state information significant for an intermediate operating state of specific intermediate operating states (ZS, CI16, CI20, BRS) occurs, and the data carrier (2) comprising detection means (46) to detect the existence of at least one operating variable (V) required for the operation of the data carrier (2), and the data carrier (2) comprising memory means (54) for storing information, the memory means (54) being designed for storing the intermediate operating state information (ZS, CI16, CI20, BRS) significant for an intermediate operating state, and the data carrier (2) comprising memory control means (51) which are designed so that after the occurrence of an intermediate operating state information (ZS, CI16, CI20, BRS) significant for an intermediate operating state they ensure that this intermediate operating state information (ZS, CI16, CI20, BRS) significant for an intermediate operating state is stored in the memory means (54), and the data carrier (2) comprising control means (51), which are designed so that—
- after the detection of the non-existence of the at least one operating variable (V) during the interrupted execution of the communication sequence due to this non-existence of the at least one operating variable (V) and the subsequent detection of the re-existence of the at least one operating variable (V) by the detection means (46)—
they ensure that the data carrier (2) is controlled in an intermediate operating state for which intermediate operating state an intermediate operating state information (ZS, CI16, CI20, BRS) stored in the memory means (54) is significant.
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Accused Products
Abstract
A data carrier (2) or an integrated circuit (41) for a data carrier (2) comprises a memory (54) which is designed to store intermediate operating state information (ZS, CI16, CI20, BRS) significant for an intermediate operating state of the data carrier (2) or the integrated circuit (41) and comprises a memory control device (51), which after the occurrence of information significant for intermediate operating states ensures that this intermediate operating state information is stored in the memory (54) and comprises a control device (51), which—after the detection of the non-existence of the supply voltage (V) required for faultless operation during execution of a communication sequence interrupted by this non-existence and the subsequent detection of the re-existence of the supply voltage (V)—ensure that the data carrier (2) or the integrated circuit (41) is controlled in an intermediate operating state for which intermediate operating state information (ZS, CI16, CI20, BRS) stored in the memory (54) is significant.
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Citations
16 Claims
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1. A data carrier (2) comprising communication means (50) for communication with at least one communication station (1) in accordance with a communication sequence executed during the communication, the communication sequence comprising several communication steps, and in the data carrier (2) an intermediate operating state occurs as a result of a communication step of specific communication steps, and in the data carrier (2) intermediate operating state information significant for an intermediate operating state of specific intermediate operating states (ZS, CI16, CI20, BRS) occurs, and the data carrier (2) comprising detection means (46) to detect the existence of at least one operating variable (V) required for the operation of the data carrier (2), and the data carrier (2) comprising memory means (54) for storing information, the memory means (54) being designed for storing the intermediate operating state information (ZS, CI16, CI20, BRS) significant for an intermediate operating state, and the data carrier (2) comprising memory control means (51) which are designed so that after the occurrence of an intermediate operating state information (ZS, CI16, CI20, BRS) significant for an intermediate operating state they ensure that this intermediate operating state information (ZS, CI16, CI20, BRS) significant for an intermediate operating state is stored in the memory means (54), and the data carrier (2) comprising control means (51), which are designed so that—
- after the detection of the non-existence of the at least one operating variable (V) during the interrupted execution of the communication sequence due to this non-existence of the at least one operating variable (V) and the subsequent detection of the re-existence of the at least one operating variable (V) by the detection means (46)—
they ensure that the data carrier (2) is controlled in an intermediate operating state for which intermediate operating state an intermediate operating state information (ZS, CI16, CI20, BRS) stored in the memory means (54) is significant. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
- after the detection of the non-existence of the at least one operating variable (V) during the interrupted execution of the communication sequence due to this non-existence of the at least one operating variable (V) and the subsequent detection of the re-existence of the at least one operating variable (V) by the detection means (46)—
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9. An integrated circuit (41) for a data carrier (2) comprising communication means (50) for communication with at least one communication station (1) in accordance with a communication sequence executed during the communication, the communication sequence comprising several communication steps, and in the integrated circuit (41) an intermediate operating state occurs as a result of a communication step of certain communication steps, and in the integrated circuit (41) intermediate operating state information significant for an intermediate operating step of specific intermediate operating states (ZS, CI16, CI20, BRS) occurs, and the integrated circuit (41) comprising detection means (46) to detect the existence of at least one operating variable (V) required for the operation of the integrated circuit (41), the integrated circuit (41), and the integrated circuit (41) comprising memory means (54) for storing information, the memory means (54) being designed for storing the intermediate operating state information (ZS, CI16, CI20, BRS) significant for an intermediate operating state, and the integrated circuit (41) comprising memory control means (51) which are designed so that after the occurrence of an intermediate operating state information (ZS, CI16, CI20, BRS) significant for an intermediate operating state they ensure that this intermediate operating state information (ZS, CI16, CI20, BRS) significant for an intermediate operating state is stored in the memory means (54), and the integrated circuit (41) comprising control means (51), which are designed so that—
- after the detection of the non-existence of the at least one operating variable (V) during the interrupted execution of the communication sequence due to this non-existence of the at least one operating variable (V) and the subsequent detection of the re-existence of the at least one operating variable (V) by the detection means (46)—
they ensure that the integrated circuit (41) is controlled in an intermediate operating state for which intermediate operating state an intermediate operating state information (ZS, CI16, CI20, BRS) stored in the memory means is significant. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16)
- after the detection of the non-existence of the at least one operating variable (V) during the interrupted execution of the communication sequence due to this non-existence of the at least one operating variable (V) and the subsequent detection of the re-existence of the at least one operating variable (V) by the detection means (46)—
Specification