Digital quadrature signal detecting circuit with simple circuit structure

• US 20020186795A1
• Filed: 06/06/2002
• Published: 12/12/2002
• Est. Priority Date: 06/07/2001
• Status: Abandoned Application

• Current Assignee: ALPS Electric Company Limited (Alps Alpine Co., Ltd.)
• Original Assignee: ALPS Electric Company Limited (Alps Alpine Co., Ltd.)
• Inventors: Ohtaki, Yukio
• Application Number:
  US10/164,951
• Publication Number:
  US 20020186795A1
• Time in Patent Office: Days
• US Class Current: 375/340
• CPC Class Codes: H04L 27/2647 Arrangements specific to the receiver only equalisation H04L27/01

Abstract

A digital quadrature signal detecting circuit constituted by a digital signal delay circuit for forming an in-phase (I) signal by delaying a digital signal outputted from an analog/digital conversion part for analog/digital converting a received signal having a non-zero center frequency by a predetermined sampling frequency, and a digital all-pass filter for forming a quadrature (Q) signal by shifting a phase of the digital signal by 90°, wherein the digital all-pass filter is an infinite impulse response digital filter having a definite group delay frequency characteristic, and the digital signal delay circuit has a signal delay amount equal to a group delay amount of the digital all-pass filter.

Claims

1. A digital quadrature signal detecting circuit, comprising:

a digital signal delay circuit for forming an in-phase signal by delaying a digital signal outputted from an analog/digital conversion part for analog/digital converting a received signal having a non-zero center frequency by a predetermined sampling frequency; and

a digital all-pass filter for forming a quadrature signal by shifting a phase of the digital signal by 90°

,

wherein the digital all-pass filter is an infinite impulse response digital filter having a definite group delay frequency characteristic, and the digital signal delay circuit has a signal delay amount equal to a group delay amount of the digital all-pass filter.

3. A digital quadrature signal detecting circuit according to claim 1, wherein the infinite impulse response digital filter includes cascaded signal processing parts of n stages, n being an integer of three or larger, each of the cascaded signal processing parts includes a first delay part, a second delay part, an adder part, a multiplier part, and a multiplier coefficient generation part, and constants of the respective parts are set so that a phase gradient number generated in a signal band with ¼

of the sampling frequency as a center becomes n−

1.

4. A digital quadrature signal detecting circuit according to claim 3, wherein in the cascaded n stage signal processing parts, the signal processing part of an odd-numbered stage from an output side is constituted by only the first delay part and the second delay part.

5. A digital quadrature signal detecting circuit according to claim 3, wherein in a case where an output of the infinite impulse response digital filter is outputted through thinning-out with order 2, an operation frequency of the infinite impulse response digital filter is selected to ½

of the sampling frequency, and the cascaded n stage signal processing parts are constructed by only the signal processing parts of even-numbered stages from an output side.

2. A digital quadrature signal detecting circuit, comprising:

a digital signal delay circuit for forming an in-phase signal by delaying one of digital signals obtained by thinning out, with order 2, a digital signal outputted from an analog/digital conversion part for analog/digital converting a received signal having a non-zero center frequency by a predetermined sampling frequency; and

a digital all-pass filter for forming a quadrature signal by shifting, by 90°

, a phase of the other of the digital signals thinned out with order 2,

wherein the digital all-pass filter is an infinite impulse response digital filter having a definite group delay frequency characteristic, and the digital signal delay circuit has a signal delay amount equal to a group delay amount of the digital all-pass filter.

6. A digital quadrature signal detecting circuit according to claim 2, wherein the infinite impulse response digital filter includes cascaded signal processing parts of n stages, n being an integer of three or larger, each of the cascaded signal processing parts includes a first delay part, a second delay part, an adder part, a multiplier part, and a multiplier coefficient generation part, and constants of the respective parts are set so that a phase gradient number generated in a signal band with 1/4 of the sampling frequency as a center becomes n−

1.

7. A digital quadrature signal detecting circuit according to claim 6, wherein in the cascaded n stage signal processing parts, the signal processing part of an odd-numbered stage from an output side is constituted by only the first delay part and the second delay part.

8. A digital quadrature signal detecting circuit according to claim 6, wherein in a case where an output of the infinite impulse response digital filter is outputted through thinning-out with order 2, an operation frequency of the infinite impulse response digital filter is selected to ½

of the sampling frequency, and the cascaded n stage signal processing parts are constructed by only the signal processing parts of even-numbered stages from an output side.