Non-volatile memory devices and methods of fabricating the same

• US 20020187609A1
• Filed: 05/30/2002
• Published: 12/12/2002
• Est. Priority Date: 06/07/2001
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Chang, Sung-Nam, Kim, Dong-Chan
• Granted Patent: US 6,891,222 B2
• Time in Patent Office: Days
• US Class Current: 438/257
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

Non-volatile memory devices and fabrication methods thereof are provided. The device includes a plurality of isolation layers formed at a semiconductor device, a plurality of stacked gates crossing over an active region between the isolation layers, and an oxidation barrier layer covering the stacked gate. Each of the stacked gates has a control gate electrode crossing over the active region, a floating gate interposed between the control gate electrode and the active region, and an inter-gate dielectric layer interposed between the control gate electrode and the floating gate. Also, the inter-gate dielectric layer has a bottom dielectric layer, an intermediate dielectric layer and a top dielectric layer which are sequentially stacked. The oxidation barrier layer is formed prior to a subsequent thermal oxidation process for curing etch damage that occurs during formation of the stacked gates.

Claims

1. A non-volatile memory device comprising:

a plurality of isolation layers formed at a semiconductor substrate, the isolation layers defining an active region;

a stacked gate crossing over the active region and the isolation layers, the stacked gate having a top surface and a sidewall, the stacked gate including a control gate electrode crossing over the active region, a floating gate interposed between the control gate electrode and the active region, and an inter-gate dielectric layer interposed between the floating gate and the control gate electrode; and

an oxidation barrier layer extending over the top surface and the sidewall of the stacked gate.

2. The non-volatile memory device of claim 1, wherein the control gate electrode comprises a polysilicon layer and a metal suicide layer that are sequentially stacked.

3. The non-volatile memory device of claim 1, wherein both edges of the floating gate are overlapped with the isolation layer along one of two orthogonal axes of the stacked gate.

4. The non-volatile memory device of claim 1, wherein the inter-gate dielectric layer comprises a bottom dielectric layer, an intermediate dielectric layer and a top dielectric layer which are sequentially stacked.

5. The non-volatile memory device of claim 4, wherein the top dielectric layer and the bottom dielectric layer are a CVD oxide layer.

6. The non-volatile memory device of claim 4, wherein the intermediate dielectric layer is a silicon nitride layer.

7. The non-volatile memory device of claim 1, wherein the oxidation barrier layer has a thickness of approximately 50 angstroms to 100 angstroms.

8. The non-volatile memory device of claim 1, wherein the oxidation barrier layer is a CVD oxide layer or a silicon oxynitride layer.

9. A method of fabricating a non-volatile memory device, comprising:

forming a plurality of isolation layers at a semiconductor substrate to define an active region;

forming a floating gate pattern covering the active region;

sequentially forming an inter-gate dielectric layer and a control gate conductive layer on the substrate having the floating gate pattern;

successively patterning the control gate conductive layer, the inter-gate dielectric layer and the floating gate pattern to form a plurality of stacked gates crossing over the active region;

forming a conformal oxidation barrier layer on the entire surface of the resultant structure where the stacked gates are formed; and

performing a thermal oxidation process to cure etch damage that occurs during formation of the stacked gates.

10. The method of claim 9, wherein the control gate conductive layer is formed of a polysilicon layer or a metal polycide layer.

11. The method of claim 9, wherein the oxidation barrier layer is formed of a CVD oxide layer.

12. The method of claim 9, wherein the oxidation barrier layer is formed to a thickness of 50 angstroms and 100 angstroms.

13. The method of claim 9, wherein performing the thermal oxidation process is followed by forming source/drain regions at the active region between the stacked gates.