Pipelined high speed data transfer mechanism

• US 20020188691A1
• Filed: 05/13/2002
• Published: 12/12/2002
• Est. Priority Date: 10/30/1997
• Status: Active Grant

• Current Assignee: CommVault Systems Incorporated
• Original Assignee: CommVault Systems Incorporated
• Inventors: Prahlad, Anand, Tyagarajan, Mahesh, Ignatius, Paul
• Granted Patent: US 7,401,154 B2
• Time in Patent Office: Days
• US Class Current: 709/208
• CPC Class Codes: G06F 11/1464 for networked environments
• CPC Class Codes: G06F 11/3495 for systems
• CPC Class Codes: G06F 12/02 Addressing or allocation; Relocation program address sequencing G06F9/00; arrangements for selecting an address in a digital store G11C8/00
• CPC Class Codes: G06F 3/0613 in relation to throughput
• CPC Class Codes: G06F 3/0656 Data buffering arrangements
• CPC Class Codes: G06F 3/0685 Hybrid storage combining heterogeneous device types, e.g. hierarchical storage, hybrid arrays
• CPC Class Codes: G06F 9/5033 considering data affinity
• CPC Class Codes: G06F 9/544 Buffers; Shared memory; Pipes
• CPC Class Codes: H04L 69/04 Protocols for data compression, e.g. ROHC

Abstract

There is disclosed in a communications system having an origination storage device and a destination storage device, a data transfer pipeline apparatus for transferring data in a sequence of N stages, where N is a positive integer grater than 1, from the origination to the destination device. The data transfer apparatus comprises dedicated memory means having a predetermined number of buffers dedicated for carrying data associated with the transfer of data from the origination storage device to the destination device; and master control means for registering and controlling processes associated with the data transfer apparatus for participation in the N stage data transfer sequence. The processes include at least a first stage process for initiating the data transfer and a last Nth stage process for completing data transfer. The first stage process is operative to allocate a buffer from the predetermined number of buffers available within the dedicated memory means for collection, processing, and sending of the data from the origination device to a next stage process. The Nth stage process is operative to receive a buffer allocated to the first stage process from the (N−1)th stage process in the data transfer sequence and to free the buffer upon processing completion and storage in the destination device to permit reallocation of the buffer. The master control means further includes monitor means for monitoring the number of buffers from the pool of buffers allocated or assigned to particular processes in the pipeline, in order to prevent allocation of further buffers to a particular process when the number of buffers currently allocated exceeds a predetermined threshold.

Claims

1. In a communications system having an origination storage device and a destination storage device, a data transfer pipeline apparatus for transferring data in a sequence of N stages, where N is a positive integer grater than 1, from said origination to said destination device, comprising:

dedicated memory means having a predetermined number of buffers dedicated for carrying data associated with the transfer of data from said origination storage device to said destination device; and

master control means for registering and controlling processes associated with said data transfer apparatus for participation in the N stage data transfer sequence, wherein said processes include at least a first stage process for initiating said data transfer and a last Nth stage process for completing data transfer, wherein said first stage process is operative to allocate a buffer from said predetermined number of buffers available within said dedicated memory means for collection, processing, and sending of said data from said origination device to a next stage process; and

wherein said last Nth stage process is operative to receive a buffer allocated to said first stage process from the (N−

1)th stage process in the data transfer sequence and to free said buffer upon processing completion and storage in the destination device to permit reallocation of said buffer,

said master control means further including monitor means for monitoring the number of buffers from said pool of buffers allocated or assigned to particular processes in said pipeline, wherein said monitor means is operative to prevent allocation of further buffers to a particular process when said number of buffers currently allocated exceeds a predetermined threshold.

2. The communications system according to claim 1, wherein said master control means for registering processes includes registering multiple instantiations of the same process in a given stage of said data transfer sequence.

3. The communications system according to claim 2, further including a network control module coupled to said master control means for initiating network agent processes to enable communications data transfer between storage devices located on different computers coupled together via a network.

4. The communications system according to claim 2, wherein said processes further include at least one intermediate stage process registered with said master control means and sequentially coupled between said first stage process and said last Nth stage process, for receiving buffers of data, processing said buffers, and sending said processed buffers of data to said next stage process.

5. The communications systems according to claim 4, wherein each said process includes an input queue for receiving or allocating a buffer and an output queue for sending or freeing a buffer.

6. The communications system according to claim 5, wherein the input queue of the ith stage process is the output queue of the (I−

1)Th stage process where I is an integer less than or equal to N.

7. The communications system according to claim 3, wherein said originating storage device resides on a first computer and said destination device resides on a second different computer, wherein the dedicated memory means having a predetermined number of dedicated buffers further comprises:

a first memory having a first pool of buffers resident on said first computer and a second memory having a second pool of buffers resident on said second computer, wherein said master control means includes a first master controller resident on said first computer, a register and controlling processes resident on said first computer, a second controller resident on said second computer for registering and controlling those processes resident on said second computer, wherein said first memory area is shared among the processes registered on said first computer and said second memory area is shared among the processes registered on said second computer.

8. The communications system according to claim 5, said dedicated memory means further includes a plurality of reader/writer semaphores, each said semaphore associated with a particular input/output queue for controlling access to the dedicated memory.

9. The communications system according to claim 8, wherein said pool of buffers in each of said first and second memory areas comprise buffers of equal size.

10. The communications system according to claim 6, wherein said at least one intermediate stage process includes:

a sequence process coupled between a single instantiation of a process for a given stage I−

1, and multiple instantiations of a same process for stage 1+1, for stamping each buffer received from said single instantiation process with a sequence number prior to sending to said multiple instantiations of processes, and

a re-sequence processor coupled to the output queue of said multiple instantiations of processes for reordering the buffer sequence received according to the sequence number to provide a correct sequencing of the buffers for further processing.

11. The communications system according to claim 1, wherein said master control means is initiated via a request message from a requesting application process, said request message including a process id, timestamp, and machine name where said requesting application is executing.

12. The communications system according to claim 7, wherein processes resident on said first computer are operable to allocate and free buffers only within said first dedicated shared memory means, and where processes resident on said second computer are operable to allocate and free buffers only within said second dedicated shared memory means.

13. The communications system according to claim 3, wherein said network is an FDDI or ATM network.

15. The communication system according to claim 14 further including a next stage compression process coupled between said first stage collection process and said plurality of network agent processors for receiving buffers sent from said collection process and compressing the data transferred in said buffers.

16. The communication system of claim 15 wherein said compressing process includes multiple instantiations thereof operating in parallel to receive and process buffer data from said first stage collection process.

17. The communication system of claim 16, further including:

a sequence process coupled between said collection process and said multiple instantiations of said compression processes for identifying each buffer received from said collection process with a sequence number; and

a re-sequence process coupled between the multiple instantiations of said compression, process and said network agents and responsive to said sequence numbers for re-ordering said buffers according to the sequence numbers.

18. The communication system according to claim 17, wherein said plurality of network agents comprise:

multiple instantiations of a network agent resident on said first computer, and second multiple instantiations of a second network agent resident on said second computer, wherein each instantiation of said network agent on each computer is uniquely associated with a corresponding instantiation of said agent on the other computer for transferring data in said dedicated buffers across the network, wherein said multiple-instantiation of said second network agent on said second computer is operable to send buffer data to said Nth stage backup/restore process for storage in said destination storage device.

20. The method according to claim 19, further comprising the step of initiating network agent processes coupled between said first stage collection process and said Nth stage backup/restore process for transfering said data buffers across a network when said first stage collection process is resident on a first computer and said backup/restore process is resident on a second computer.

14. In a communications system having an origination storage device resident on a first computer and a destination storage device resident on a second computer, a data transfer pipeline apparatus for transferring data from said first storage device to said second storage device in a sequence of N stages for data archival, where N is a positive integer greater than 1, comprising:

dedicated memory means comprising a first memory resident on the first computer being a pool of buffers dedicated for carrying data associated with said origination storage device to said destination device and a second memory resident on the second computer; and

master control means for registering and initiating processes associated with said data transfer apparatus for partcipation in the N stage data transfer sequence, wherein said processes include;

a first stage collection process resident on said first computer and operative to allocate a sequence of buffers from said pool of buffers within said dedicated memory means for collection, processing, and sending of said data in said allocated buffers, wherein said allocated buffers are assigned to said process currently operating thereon such that said buffers are unavailable for further allocation until freed by the process to which said buffers are assigned;

an Nth stage backup/restore process resident on said second computer for receiving said sequence of buffers and assigning thereto, storing the data resident in said buffers in said destination storage device, and freeing said buffers so that they may be reallocated;

said master control means further including monitor means for monitoring the number of buffers from said pool of buffers allocated or assigned to particular processes in said pipeline wherein said monitor means is operative to prevent allocation of further buffers to a particular process when said number of buffers currently allocated exceeds a predetermined threshold; and

a network control means responsive to said master control means for initiating a plurality of network agent processes coupled between said first stage collection process and said Nth stage backup process to enable data transfer between said processes located on different computers and coupled together via a network, wherein said dedicated data memory means is shared among each of the processes participating in said data transfer pipeline.

19. In a communications system having an origination storage device and a destination storage device, a method for transferring data in a pipelined sequence of N stages, where N is a positive integer greater than 1, from said origination device to said destination device comprising the steps of:

providing dedicated memory means, comprising a pool of buffers dedicated for carrying data associated with said origination storage device to said destination device;

registering and initiating processes for participation in the N stage data transfer sequence including providing a first stage collection process;

sequentially allocating buffers to said collection process from said pool buffers within said dedicated memory, wherein said allocated buffers are assigned to said process currently operating thereon such that said buffers are unavailable for further allocation until freed by a process to which said buffers are assigned to providing an Nth stage backup/restore process for receiving said sequence of buffers;

assigning said sequence of buffers to said Nth stage process;

storing the data resident in said buffers in said destination storage device;

freeing said assigned buffers for reallocation and re-entry into said pool of available buffers;

and monitoring the number of buffers allocated and assigned to each process in said pipeline and preventing further allocation of buffers from said pool of buffers when the number of buffers currently allocated to a particular process exceeds a predetermined threshold.