Analog MOS semiconductor device, manufacturing method therefor, manufacturing program therefor, and program device therefor

• US 20020190279A1
• Filed: 03/27/2002
• Published: 12/19/2002
• Est. Priority Date: 04/02/2001
• Status: Active Grant

• Current Assignee: Panasonic Corporation (Panasonic Holdings Corporation)
• Original Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Inventors: Nakatsuka, Junji
• Granted Patent: US 6,732,334 B2
• Time in Patent Office: Days
• US Class Current: 257/204
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique

Abstract

In an analog MOS semiconductor device, each of a plurality of MOS transistors includes a plurality of micro-unit transistors. In this way, even if a process error occurs in a transistor, a systematic offset voltage and a random offset voltage are suppressed to low levels. The micro-unit transistor has a channel width that is obtained by dividing, by an integer, a smallest channel width among those of the plurality of MOS transistors. Each micro-unit transistor includes two small transistors connected in parallel to each other, including a shared drain located in a central position, gates located on opposite sides of the drain, and sources located respectively on the outer side of the gates, i.e., at opposite ends of the micro-unit transistor.

Claims

1. An analog MOS semiconductor device, comprising a plurality of MOS transistors, wherein:

a transistor having a channel width that is obtained by dividing, by an integer, a smallest channel width among those of the plurality of MOS transistors is used as a micro-unit transistor; and

each of the plurality of MOS transistors includes a plurality of micro-unit transistors.

2. The analog MOS semiconductor device of claim 1, wherein:

the plurality of MOS transistors include two types of MOS transistors of P-type MOS transistors and N-type MOS transistors; and

the micro-unit transistors include two types of micro-unit transistors of P-type micro-unit transistors and N-type micro-unit transistors.

3. The analog MOS semiconductor device of claim 2, wherein each of MOS transistors that are included in a conditional expression for realizing zero systematic offset voltage includes a number of micro-unit transistors that satisfies the conditional expression for realizing zero systematic offset voltage.

4. The analog MOS semiconductor device of claim 1, wherein the micro-unit transistors of each MOS transistor overlap with one another.

5. The analog MOS semiconductor device of claim 1, wherein:

each micro-unit transistor includes an even number of small transistors;

the even number of small transistors are connected in parallel to one another; and

two of the even number of small transistors connected in parallel to one another that are located at opposite ends each have a source located at one end of the micro-unit transistor.

6. The analog MOS semiconductor device of claim 5, wherein:

the micro-unit transistor is a pair transistor including two small transistors connected in parallel to each other; and

a source of one of the small transistors is located at one end of the pair transistor, and a source of the other one of the small transistors is located at the other end of the pair transistor.

7. The analog MOS semiconductor device of claim 1, 2, 3, 4, 5 or 6, wherein the micro-unit transistor includes a substrate contact via which one or more of electrodes of the micro-unit transistor is connected to a semiconductor substrate.

8. The analog MOS semiconductor device of claim 1, 2, 3, 4, 5 or 6, wherein the micro-unit transistor includes a gate contact connected to a gate of the micro-unit transistor, and a gate wire connected to the gate contact for applying a gate voltage to the gate.

9. The analog MOS semiconductor device of claim 1, 2, 3, 4, 5 or 6, wherein dummy micro-unit transistors are provided for adjusting a power of one or more of the plurality of MOS transistors.

10. The analog MOS semiconductor device of claim 9, wherein the dummy micro-unit transistors include two types of dummy micro-unit transistors of P-type dummy micro-unit transistors and N-type dummy micro-unit transistors.

11. The analog MOS semiconductor device of claim 1, 2, 3, 4, 5 or 6, wherein two MOS transistors forming a pair, among the plurality of MOS transistors, each include a number of micro-unit transistors that is a multiple of four.

12. The analog MOS semiconductor device of claim 1, 2, 3, 4, 5 or 6, wherein the plurality of MOS transistors have an SOI structure or an SOS structure.

14. The method for manufacturing an analog MOS semiconductor device of claim 13, wherein if the plurality of MOS transistors include two types of MOS transistors of P-type MOS transistors and N-type MOS transistors, two types of micro-unit transistors of P-type micro-unit transistors and N-type micro-unit transistors are prepared as the micro-unit transistors, so that each P-type MOS transistor includes more than one of the P-type micro-unit transistors and each N-type MOS transistor includes more than one of the N-type micro-unit transistors.

15. The method for manufacturing an analog MOS semiconductor device of claim 14, wherein when manufacturing MOS transistors that are included in a conditional expression for realizing zero systematic offset voltage, the number of micro-unit transistors to be included in each of the MOS transistors is set to be a number that satisfies the conditional expression for realizing zero systematic offset voltage.

17. A program device, comprising the manufacturing program of claim 16, wherein the program device has an EDA function or a CAD function for manufacturing an analog MOS semiconductor device including a plurality of MOS transistors based on the manufacturing program.

13. A method for manufacturing an analog MOS semiconductor device including a plurality of MOS transistors, comprising the steps of:

preparing a plurality of micro-unit transistors each having a channel width that is obtained by dividing, by an integer, a smallest channel width among those of the plurality of MOS transistors; and

manufacturing the plurality of MOS transistors using the plurality of micro-unit transistors so that each of the plurality of MOS transistors includes more than one of the micro-unit transistors.

16. A program for manufacturing an analog MOS semiconductor device including a plurality of MOS transistors, the program comprising the steps of:

defining, as a micro-unit transistor, a transistor having a channel width that is obtained by dividing, by an integer, a smallest channel width among those of the plurality of MOS transistors; and

designing the plurality of MOS transistors so that each of the plurality of MOS transistors includes a plurality of micro-unit transistors.