Semiconductor device with borderless contact structure and method of manufacturing the same

• US 20020190316A1
• Filed: 06/14/2002
• Published: 12/19/2002
• Est. Priority Date: 06/19/2001
• Status: Abandoned Application

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kwean, Sung-Un, Hwang, Jae-Seung
• Application Number:
  US10/172,354
• Publication Number:
  US 20020190316A1
• Time in Patent Office: Days
• US Class Current: 257/344
• CPC Class Codes: H01L 21/76802 by forming openings in dielectrics
• CPC Class Codes: H01L 21/76832 Multiple layers
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665

Abstract

A semiconductor device comprising a borderless contract structure and a method of manufacturing the same. An etch-protecting layer is formed on a semiconductor substrate having gate electrodes formed on an active area of the substrate. Spacers are formed on the etch-protecting layer, and removed after performing a source/drain ion-implantation process to secure a region for forming a contact hole between the gate electrodes. After sequentially forming an etch-stopping layer and an insulating interlayer on a resultant structure, the etch-stopping layer and the insulating interlayer are etched to form the first contact hole which exposes a surface of the semiconductor substrate between gate electrodes and a second contact hole for the borderless contact which exposes the surface of the semiconductor substrate adjacent to the field oxide layer and a portion of a surface of the field oxide layer.

Claims

1. A semiconductor device, comprising:

a semiconductor substrate comprising an active area and a field area, the active and field areas being divided by a field oxide layer;

a plurality of gate electrodes formed on the active area of the semiconductor substrate;

an etch-protecting layer formed on the gate electrodes and the semiconductor substrate;

an etch-stopping layer stacked on the etch-protecting layer; and

an insulating interlayer formed on the etch-stopping layer comprising a first contact hole passing through the etch-protecting layer and the etch-stopping layer to expose a surface of the semiconductor substrate formed between gate electrodes and a second contact hole passing through the etch-protecting layer and the etch-stopping layer to expose a surface of the semiconductor substrate adjacent to the field oxide layer and a portion of a surface of the field oxide layer, thereby forming a borderless contact between the active area and the field area;

wherein the etch-protecting layer and the etch-stopping layer protect the gate electrodes and the semiconductor substrate during an etching process of forming the first and second contact holes such that an enlarged width between the gate electrodes is obtained without forming spacers between the gate electrodes.

2. The device of claim 1, further comprising highly doped source and drain areas in the active area of the semiconductor substrate.

3. The device of claim 1, wherein a thickness of the etch-stopping layer formed on the field oxide layer and a thickness of the etch-stopping layer formed between the gate electrodes are uniform.

4. The device of claim 1, wherein the etch-stopping layer comprises a material similar to a material of the insulating inter layer to prevent formation of a recess on the field oxide layer.

5. The device of claim 1, wherein the etch-protecting layer comprises a material similar to a material of the etch-stopping layer.

6. The device of claim 5, wherein the etch-protecting layer comprises a nitride.

7. The device of claim 6, wherein the etch-protecting layer has a thickness in the range of about 50 to about 300 Å

, and the etch-stopping layer has a thickness in the range of about 100 to about 100Å

.

8. The device of claim 5, further comprising a buffer layer formed between the semiconductor substrate on which the gate electrodes formed and the etch-protecting layer, the buffer layer comprising an oxide.

9. The device of claim 1, wherein the etch-protecting layer comprises an oxide and has a thickness in the range of about 50 to about 300Å

.

10. The device of claim 9, wherein the etch-stopping layer comprises a nitride and has a thickness greater than 300Å

.

11. A method for forming a contact hole of a semiconductor device, the method comprising the steps of:

forming a plurality of gate electrodes on an active area of a semiconductor substrate, the semiconductor substrate comprising the active area and a field area divided by a field oxide layer;

forming an etch-protecting layer on the gate electrodes and the semiconductor substrate;

forming spacers on the etch-protecting layer formed on both sides of each gate electrode, the spacers comprising a material having an etch selectivity with respect to the etch-protecting layer;

performing a source and drain ion-implantation process by using the gate electrodes on which the spares are formed as a mask;

removing the spacers;

forming an etch-stopping layer on the entire surface of the resultant structure;

forming an insulating interlayer on the etch-stopping layer; and

sequentially etching the insulating interlayer, the etch-stopping layer and the etch-protecting layer such that a first contact hole is formed to expose a surface of the semiconductor substrate between the gate electrodes and a second contact hole is formed to expose a surface of the semiconductor substrate adjacent to the field oxide layer and a portion of a surface of the field oxide layer, thereby forming a borderless contact between the field area and the active area.

12. The method of claim 11, wherein the step of forming the insulating interlayer comprises the step of forming the insulating interlayer with a material similar to a material of the etch-stopping to prevent formation of a recess on the filed oxide layer.

13. The method of claim 11, wherein the step of forming the etch-stopping layer comprises the step of forming the etch-stopping layer such that a thickness of the etch-stopping layer formed on the field oxide layer and a thickness of the etch-stopping layer formed between the gate electrodes are uniform.

14. The method of claim 11, wherein the etch-protecting layer comprises an oxide and the spacers comprises polysilicon.

15. The method of claim 14, wherein the step of removing the spacers comprising the step of performing a wet etching process using etchant in which an etch selectivity of the polysilicon with respect to the oxide is about 30:

1.

16. The method of claim 14, wherein the etch-protecting layer has a thickness in the range of about 50 to about 300Å

.

17. The method of claim 11, wherein the step of forming the etch-stopping layer comprises the step of depositing a nitride to a thickness greater than 300Å

.

19. The method of claim 18, further comprising the step of performing an ion-implantation using the gate electrodes as a mask to form lightly doped source and drain areas before the step of forming the etch-protecting layer.

20. The method of claim 18, wherein the step of forming the etch-protecting layer comprises the step of depositing a nitride on the gate electrodes and the semiconductor substrate and the step of forming the spacers comprise the step of depositing an oxide on the etch-protecting layer.

21. The method of claim 20, wherein the nitride comprises one of SiN, SiON, and BN.

22. The method of claim 20, wherein the step of removing the spacers comprises the step of performing a wet etching process using etchant in which an etch selectivity of the oxide of the spacers with respect to the nitride of the etch-protecting layer is about 20:

1.

23. The method of claim 20, wherein the step of forming the etch-protecting layer comprises the step of forming the etch-protecting layer to have a thickness capable of reducing a blocking effect of the step of performing the source/drain ion-implantation process.

24. The method of claim 23, wherein the etch-protecting layer has a thickness in the range of about 50 to about 300Å

.

25. The method of claim 18, wherein the step of forming the etch-stopping layer comprises the step of forming the etch-stopping layer to have a thickness in the range of about 100 to about 1000Å

.

26. The method of claim 20, further comprising the step of depositing an oxide on the gate electrodes and the semiconductor substrate to form a buffer layer before the step of depositing the nitride to form the etch-protecting layer.

27. The method of claim 26,wherein the buffer layer has a thickness in the range of about 30 to about 100Å

.

18. A method for forming a contact hole of a semiconductor device, the method comprising the steps of:

forming a plurality of gate electrodes on an active area of a semiconductor substrate, the semiconductor substrate comprising the active area and a field area divided by a field oxide layer;

forming an etch-protecting layer on the gate electrodes and the semiconductor substrate;

forming spacers on the etch-protecting layer formed on both sides of each gate electrode, the spacers comprising a material having an etch selectivity with respect to the etch-protecting layer;

performing a source and drain ion-implantation process by using the gate electrodes on which the spares are formed as a mask;

removing the spacers;

forming an etch-stopping layer on the entire surface of the resultant structure, wherein the etch-stopping layer comprising a material similar to a material of the etch-protecting layer;

forming an insulating interlayer on the etch-stopping layer; and

sequentially etching the insulating interlayer, the etch-stopping layer and the etch-protecting layer, such that a first contact hole is formed to expose a surface of the semiconductor substrate between the gate electrodes and a second contact hole is formed to expose a surface of the semiconductor substrate adjacent to the field oxide layer and a portion of a surface of the field oxide layer, thereby forming a borderless contact between the field area and the active area.