Semiconductor device and method of manufacturing same

• US 20020190349A1
• Filed: 07/30/2002
• Published: 12/19/2002
• Est. Priority Date: 04/19/2000
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Yamaguchi, Yasuo, Maeda, Shigenobu, Matsumoto, Takuji, Ipposhi, Takashi, Hirano, Yuuichi
• Granted Patent: US 6,611,041 B2
• Time in Patent Office: Days
• US Class Current: 257/531
• CPC Class Codes: H01L 21/28518 the conductive layers comprising silicides H01L21/28537 takes precedence
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 23/645 Inductive arrangements H01L23/647, H01L23/66 take precedence
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/08 including only semiconductor components of a single kind
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A semiconductor device having an inductor is provided. In an RF circuit portion (RP), a region in an SOI layer (3) corresponding to a region in which a spiral inductor (SI) is provided is divided into a plurality of SOI regions (21) by a plurality of trench isolation oxide films (11). The trench isolation oxide films (11) are formed by filling trenches extending from the surface of the SOI layer (3) to the surface of a buried oxide film (2) with a silicon oxide film, and completely electrically isolate the SOI regions (21) from each other. The trench isolation oxide films (11) have a predetermined width and are shaped to extend substantially perpendicularly to the surface of the buried oxide film (2). The semiconductor device is capable of reducing electrostatically induced power dissipation and electromagnetically induced power dissipation, and preventing the structure and manufacturing steps thereof from becoming complicated.

Claims

1. A semiconductor device comprising:

a semiconductor substrate;

a shield layer disposed in a main surface of said semiconductor substrate; and

an inductance element disposed over a region in which said shield layer is formed, with an interlayer insulation film therebetween;

wherein said shield layer has at least one conductive portion connected to a ground potential, and at least one current interrupting portion for interrupting a path of an eddy current induced by said inductance element in a plane of said at least one conductive portion.

2. The semiconductor device according to claim 1,

wherein said semiconductor substrate is an SOI substrate comprising a substrate portion serving as a foundation, a buried oxide film disposed on said substrate portion, and an SOI layer disposed on said buried oxide film;

wherein said at least one current interrupting portion comprises a plurality of selectively disposed isolation oxide films extending from a surface of said SOI layer through said SOI layer to said buried oxide film; and

wherein said at least one conductive portion comprises a plurality of SOI regions electrically isolated from each other by said plurality of isolation oxide films.

3. The semiconductor device according to claim 2,

wherein each of said plurality of isolation oxide films has a predetermined width and extends substantially perpendicularly to a surface of said buried oxide film.

4. The semiconductor device according to claim 2,

wherein each of said plurality of isolation oxide films includes a first portion having a first width and extending substantially perpendicularly to a surface of said buried oxide film, and a second portion continuous with and beneath said first portion, said second portion having a second width smaller than said first width and extending substantially perpendicularly to the surface of said buried oxide film.

5. The semiconductor device according to claim 1,

wherein said semiconductor substrate is an SOI substrate comprising a substrate portion serving as a foundation, a buried oxide film disposed on said substrate portion, and an SOI layer disposed on said buried oxide film;

wherein said at least one conductive portion comprises a plurality of SOI regions obtained by thinning said SOI layer to a predetermined thickness; and

wherein said at least one current interrupting portion comprises an insulation film disposed to at least fill a space between said plurality of SOI regions.

6. The semiconductor device according to claim 5,

wherein each of said plurality of SOI regions contains a semiconductor impurity of a relatively high concentration.

7. The semiconductor device according to claim 5,

wherein each of said plurality of SOI regions has a silicide film formed on an upper surface thereof.

8. The semiconductor device according to claim 1,

wherein said semiconductor substrate is an SOI substrate comprising a substrate portion serving as a foundation, a buried oxide film disposed on said substrate portion, and an SOI layer disposed on said buried oxide film;

wherein said shield layer comprises

a first group of SOI regions of a first conductivity type, and

a second group of SOI regions of a second conductivity type,

said first group of SOI regions and said second group of SOI regions being combined to constitute a plurality of diodes;

wherein said at least one current interrupting portion includes at least one reverse-biased diode which is at least one of said plurality of diodes to which a reverse bias is applied; and

wherein said at least one conductive portion includes one of said first and second groups connected to a ground potential.

9. The semiconductor device according to claim 8,

wherein said first group of SOI regions and said second group of SOI regions are formed in a region obtained by thinning said SOI layer to a predetermined thickness,

said semiconductor device further comprising

an isolation oxide film for entirely covering said first group of SOI regions and said second group of SOI regions.

10. The semiconductor device according to claim 8,

wherein each of said first group of SOI regions includes a first region approximately equal in thickness to said SOI layer, and a second region adjacent to said first region and obtained by thinning said SOI layer;

and

wherein each of said second group of SOI regions is approximately equal in thickness to said SOI layer;

said semiconductor device further comprising

an isolation oxide film for covering an upper surface of each of said second regions.

11. The semiconductor device according to claim 10,

wherein each of said first regions of said first group of SOI regions and said second group of SOI regions has a silicide film formed on an upper surface thereof.

12. The semiconductor device according to claim 8,

wherein each of said first group of SOI regions is a region obtained by thinning said SOI layer to a predetermined thickness;

wherein each of said second group of SOI regions is approximately equal in thickness to said SOI layer; and

wherein said first group of SOI regions and said second group of SOI regions are adjacent to each other;

said semiconductor device further comprising

an isolation oxide film for individually covering said first group of SOI regions.

13. The semiconductor device according to claim 12,

wherein each of said second group of SOI regions has a silicide film formed on an upper surface thereof.

14. The semiconductor device according to claim 12,

wherein said second group of SOI regions are of a rectangular plan configuration;

and

wherein said shield layer is of a plan configuration in which said second group of SOI regions are arranged in a matrix, with said isolation oxide film therebetween.

15. The semiconductor device according to claim 12,

wherein said second group of SOI regions are electrically connected to each other by a gate interconnect line similar in construction to a gate electrode of a MOS transistor.

16. The semiconductor device according to claim 8,

wherein said first group of SOI regions and said second group of SOI regions are arranged in an alternating pattern;

and

wherein a gate structure of a MOS transistor is disposed on each of said first group of SOI regions.

17. The semiconductor device according to claim 8,

wherein said first group of SOI regions and said second group of SOI regions are arranged in an alternating pattern;

wherein each of said first group of SOI regions includes a first region and a second region adjacent to said first region; and

wherein a gate structure of a MOS transistor is disposed on each of said second regions.

18. The semiconductor device according to claim 8,

wherein said first group of SOI regions and said second group of SOI regions are arranged in an alternating pattern;

wherein each of said first group of SOI regions includes a first region and a second region adjacent to said first region; and

wherein each of said second group of SOI regions and said first regions has a silicide film formed thereon selectively for non-engagement with said second regions.

19. The semiconductor device according to claim 8,

wherein said first group of SOI regions and said second group of SOI regions are arranged in an alternating pattern;

and

wherein each of said first group of SOI regions has a silicide film formed thereon selectively for non-engagement with said second group of SOI regions.