Method of testing semiconductor integrated circuits and testing board for use therein

• US 20020190743A1
• Filed: 04/23/2002
• Published: 12/19/2002
• Est. Priority Date: 09/04/1997
• Status: Abandoned Application

• Current Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Original Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Inventors: Oki, Shinichi, Nakata, Yoshiro
• Application Number:
  US10/127,580
• Publication Number:
  US 20020190743A1
• Time in Patent Office: Days
• US Class Current: 324/750.05
• CPC Class Codes: G01R 31/2886 Features relating to contacting the IC under test, e.g. probe heads; chucks G01R31/2865 takes precedence, test connections, e.g. test sockets, or probes per se, G01R1/04 or G01R1/06

Abstract

A method of testing semiconductor integrated circuits comprises the step of simultaneously testing a plurality of semiconductor integrated circuit elements for electric characteristics by applying a voltage to the respective testing electrodes of the semiconductor integrated circuit elements. The simultaneous testing step includes the step of applying the voltage to the respective testing electrodes of the semiconductor integrated circuit elements via PTC elements provided for the semiconductor integrated circuit elements in a one-to-one relationship.

Claims

1. A method of testing semiconductor integrated circuits, comprising the steps of:

simultaneously testing a plurality of semiconductor integrated circuit elements for electric characteristics by applying a voltage to respective testing electrodes of said semiconductor integrated circuit elements,

said step including the step of applying the voltage to the respective testing electrodes of the semiconductor integrated circuit elements via at least one PTC element; and

wherein said step includes the step of applying the voltage to the respective testing electrodes of said semiconductor integrated circuit elements via the plurality of PTC elements provided in a one-to-one relationship for individual blocks formed by dividing said semiconductor integrated circuit elements into groups.

2. A method of testing semiconductor integrated circuits, comprising the steps of:

simultaneously testing a plurality of semiconductor integrated circuit elements for electric characteristics by applying a voltage to respective testing electrodes of said semiconductor integrated circuit elements,

said step including the step of applying the voltage to the respective testing electrodes of the semiconductor integrated circuit elements via at least one PTC element;

wherein said plurality of semiconductor integrated circuit elements are mounted on a bum-in board and said step includes the step of performing a simultaneous bum-in process with respect to said semiconductor integrated circuit elements.