Display apparatus, digital-to-analog conversion circuit and digital-to-analog conversion method

• US 20020190971A1
• Filed: 04/26/2002
• Published: 12/19/2002
• Est. Priority Date: 04/27/2001
• Status: Active Grant

• Current Assignee: Japan Display Central Incorporated (Japan Display Incorporated)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Nakamura, Kazuo, Nakamura, Takashi, Fujiwara, Hisao, Karube, Masao, Hayashi, Hirotaka, Kitani, Masakatsu
• Granted Patent: US 7,136,058 B2
• Time in Patent Office: Days
• US Class Current: 345/204
• CPC Class Codes: G09G 2300/0408 Integration of the drivers onto the display substrate
• CPC Class Codes: G09G 2310/0248 Precharge or discharge of column electrodes before or after applying exact column voltages
• CPC Class Codes: G09G 2310/027 Details of drivers for data electrodes, the drivers handling digital grey scale data, e.g. use of D/A converters
• CPC Class Codes: G09G 2310/0291 Details of output amplifiers or buffers arranged for use in a driving circuit
• CPC Class Codes: G09G 2310/0297 Special arrangements with multiplexing or demultiplexing of display data in the drivers for data electrodes, in a pre-processing circuitry delivering display data to said drivers or in the matrix panel, e.g. multiplexing plural data signals to one D/A converter or demultiplexing the D/A converter output to multiple columns
• CPC Class Codes: G09G 2320/0233 Improving the luminance or brightness uniformity across the screen
• CPC Class Codes: G09G 2330/02 Details of power systems and of start or stop of display operation
• CPC Class Codes: G09G 2330/021 Power management, e.g. power saving
• CPC Class Codes: G09G 3/2011 by amplitude modulation
• CPC Class Codes: G09G 3/3688 suitable for active matrices only
• CPC Class Codes: H03M 1/804 with charge redistribution

Abstract

A signal line drive circuit according to the present invention has: a latch circuit which latches digital pixel data; a D/A converter which converts a latch output from the latch circuit into an analog video signal; an AMP which amplifies the analog video signal converted by the D/A converter; and a signal selection circuit which selects a signal line to which the analog video signal amplified by the AMP is supplied. The AMP has: an odd number of inverters which are cascade-connected; capacitor elements which are respectively connected between stages of the inverters and between an input terminal of the inverter on a first stage and an output terminal of the inverter on a last stage; a first power supply line which supplies a power supply voltage to the inverter on the first stage; and a second power supply line which supplies a power supply voltage to inverters other than the inverter on the first stage. The accuracy of the AMP can be improved by separating the power supply line for only the inverter on the first stage.

Claims

1. A display apparatus comprising:

signal lines and scanning lines which are vertically and horizontally provided in rows on an insulation substrate;

display elements formed in the vicinity of the respective intersections of said signal lines and said scanning lines;

a scanning line drive circuit which drives said scanning lines; and

a signal line drive circuit which is formed on said insulation substrate and drives said signal lines,

said signal line drive circuit having;

an amplifier which amplifies an analog video signal; and

a signal line selection circuit which selects a signal line to which said analog video signal amplified in said amplifier is supplied,

said amplifier having;

an odd number of inverters which are cascade-connected;

first capacitor elements each of which is connected between stages of said inverters and between an input terminal of said inverter on a first stage and an output terminal of said inverter on a last stage;

a first power supply line which supplies a power supply voltage to said inverter on said first stage; and

a second power supply line which supplies a power supply voltage to said inverters on stages other than said first stage.

2. The display apparatus according to claim 1, further comprising impedance elements which are individually inserted to said first and second power supply lines.

3. A display apparatus comprising:

signal lines and scanning lines which are vertically and horizontally provided in rows on an insulation substrate;

display elements which are formed in the vicinity of the respective intersections of said signal lines and said scanning lines;

a scanning drive circuit which drives said scanning lines; and

a signal line drive circuit which is formed on said insulation substrate and drives said signal lines,

said signal line drive circuit having;

an amplifier which amplifies an analog video signal; and

a signal line selection circuit which selects a signal lines to which said analog video signal amplified by said amplifier is supplied,

said signal line selection circuit having a plurality of analog switches connected in parallel in accordance with each signal line,

a plurality of said analog switches corresponding to the same signal line being controlled to be turned on/off in the same direction.

4. The display apparatus according to claim 3, further comprising impedance elements which are inserted between said signal lines and a plurality of said corresponding analog switches in accordance with each of said signal lines.

5. A display apparatus comprising:

signal lines and scanning lines which are vertically and horizontally provided in rows on an insulation substrate;

display elements which are formed in the vicinity of the respective intersections of said signal lines and said scanning lines;

analog switches formed on said insulation substrate; and

punch-through compensation analog switches which are respectively connected to at least some of said analog switches in series and controlled to be turned on/off in directions opposed to those of said corresponding analog switches,

each of said punch-through compensation analog switches having a pMOS transistor and an nMOS transistor connected in parallel, and a source and a drain of each of said both transistors being short-circuited.

6. A display apparatus comprising:

signal lines and scanning lines vertically and horizontally provided in rows on an insulation substrate;

display elements which are formed in the vicinity of the respective intersections of said signal lines and said scanning lines;

a scanning line drive circuit which drives said scanning lines; and

a signal line drive circuit which is formed on said insulation substrate and drives said signal lines,

said signal line drive circuit having;

an amplifier which amplifies an analog video signal; and

a signal line selection circuit which selects a signal line to which said analog video signal amplified by said amplifier is supplied,

said amplifier having;

a power supply line and a ground line;

three inverters which are cascade-connected;

resistance elements provided between said inverters and said power supply line;

resistance elements provided between said inverters and said ground line;

a first capacitor element which is connected between an input terminal of said inverter on a first stage and an output terminal of said inverter on a last stage;

a switching circuit which is provided to said inverter on said first stage and capable of switching whether input and output terminals of said inverter on said first stage are short-circuited; and

a phase compensation impedance element which is inserted between input and output terminals of said inverter on a second stage.

7. The display apparatus according to claim 6, wherein said amplifier has:

capacitor elements respectively connected between said three inverters which are cascade-connected; and

switching circuits each of which is provided to said respective three inverters and capable of switching whether input and output terminals of a corresponding inverter are short-circuited.

8. The display apparatus according to claim 6, wherein a product of a resistance value and a capacitance value of said phase compensation impedance element is substantially equal to a value of a product of a signal line load capacitance and a signal line resistance.

9. The display apparatus according to claim 6, wherein a value of said inverter (gate width/gate length) on a second stage is larger than a value of said inverter on a third stage.

10. A display apparatus comprising:

an insulation substrate having signal lines and scanning lines which are vertically and horizontally provided in rows, display elements which are formed in the vicinity of the respective intersections of said signal lines and said scanning lines, a scanning line drive circuit which drives said scanning lines, a signal line drive circuit which is formed on said insulation substrate and drives said signal lines;

an opposed substrate which is oppositely arranged on said insulation substrate and to which a common electrode is formed,

said signal line drive circuit having;

an amplifier which amplifies an analog video signal; and

a signal line selection circuit which selects a signal line to which said analog video signal amplified by said amplifier is supplied,

said amplifier having an odd number of inverters which are cascade-connected and maximizing a gain of each inverter in the vicinity of a voltage where the inclination of a voltage-brightness characteristic curve of said display elements becomes maximum.

11. The display apparatus according to claim 10, wherein said amplifier is constituted by cascade-connecting odd number of inverters, and each of said inverters is a complementary inverter having a pMOS transistor and an nMOS transistor which are connected between first and second power supply voltages in series.

13. The display apparatus according to claim 12, wherein a size of said transistor is a ratio of a gate width of said transistor relative to a gate length of the same.

17. The display apparatus according to claim 16, wherein each of a plurality of said first amplification portions has first and second inverters connected in parallel,

said selection portion having:

a first switching portion which switches whether an output terminal of said first inverter and an input terminal of said second amplification portion are connected with said capacitor element sandwiched therebetween;

a second switching portion which switches whether an input terminal of said first inverter and an output terminal of said second amplification portion are connected with said capacitor element sandwiched therebetween;

a third switching portion which switches whether an output terminal of said second inverter and an input terminal of said second amplification portion are connected with said capacitor element sandwiched therebetween;

a fourth switching portion which switches whether an input terminal of said second inverter and an output terminal of said second amplification are connected with said capacitor element sandwiched therebetween,

said amplifier alternately performing formation of a closed loop including said first inverter and formation of a closed loop including said second inverter every time said signal line selection circuit performs signal line writing.

18. The display apparatus according to claim 16, wherein, immediately after supplying an output from one of said first and second inverters to said second amplification portion by turning on said second or fourth switching portion, an analog video signal which is to be subsequently written is supplied to the other one of said first and second inverters by turning on said first or third switching portion.

20. The display apparatus according to claim 19, wherein a digital circuit component in said signal line drive circuit is driven with said second power supply voltage.

21. The display apparatus according to claim 19, wherein said amplifier has:

capacitor elements respectively connected between stages of three inverters which are cascade-connected;

switching circuits each of which is provided in accordance with each of said three inverters and capable of switching whether input and output terminals of a corresponding inverter is short-circuited;

a first impedance element connected between said second power supply line and a first power supply terminal of each of said odd number of inverters; and

a second impedance element which is connected between a ground potential line and a second power supply terminal of each of said odd number of inverters, and has an impedance smaller than that of said first impedance element.

12. A display apparatus comprising:

signal lines and scanning lines which are vertically and horizontally provided in rows on an insulation substrate;

display elements which are formed in the vicinity of the respective intersections of said signal lines and said scanning lines;

a scanning line drive circuit which drives said scanning lines; and

a signal line drive circuit which is formed on said insulation substrate and drives said signal lines,

said signal line drive circuit having;

an amplifier which amplifies an analog video signal; and

a signal line selection circuit which selects a signal line to which said analog video signal amplified by said amplifier is supplied,

said amplifier having inverters on (2n+1) stages (where n is an integer not less than

     1) which are cascade-connected, and capacitor elements respectively connected between said (2n+1) stages of said inverters and between an input terminal of said inverter on a first stage and an output terminal of said inverter on a last stage,

a size of each transistor constituting said inverters from a second stage to a 2n-th stage being equal to or larger than a size of a transistor constituting said inverter on a last stage, and a size of each transistor constituting said inverter on a first stage being equal to or smaller than a size of a transistor constituting said inverter on said second stage.

14. A display apparatus comprising:

signal lines and scanning lines which are vertically and horizontally provided in rows on an insulation substrate;

display elements which are formed in the vicinity of the respective intersections of said signal lines and said scanning lines;

a scanning line drive circuit which drives said scanning lines; and

a signal line drive circuit which is formed on said insulation substrate and drives said signal lines,

said signal line drive circuit having;

an amplifier which amplifies an analog video signal; and

a signal line selection circuit which selects a signal line to which said analog video signal amplified by said amplifier is supplied,

said amplifier having;

a power supply line and a ground line;

inverters on (2n+1) stages (where n is an integer not less than

     1) which are cascade-connected;

capacitor elements which are respectively connected between said (2n+1) stages of said inverters and between an input terminal of said inverter on a first stage and an output terminal of said inverter on a last stage; and

a plurality of impedance elements respectively connected to said power supply line and said odd number of inverters,

an impedance value of said impedance elements respectively connected to said inverters from a second stage to a 2n-th stage being not more than an impedance value of said impedance element connected to said inverter on a last stage, and an impedance value of said impedance element connected to said inverter on a first stage being not less than an impedance value of said impedance element connected to said inverter on said second stage.

15. A display apparatus comprising:

signal lines and scanning lines which are vertically and horizontally provided in rows on an insulation substrate;

display elements which are formed in the vicinity of the respective intersections of said signal line and said scanning line;

a scanning line drive circuit which drives said scanning lines; and

a signal line drive circuit which is formed on said insulation substrate and drives said signal lines,

said signal line drive circuit having;

a latch circuit which latches digital pixel data;

a D/A converter which converts a latch output from said latch circuit into an analog video signal;

an amplifier which amplifies said analog video signal converted by said D/A converter; and

a signal line selection circuit which selects a signal line to which said analog video signal amplified by said amplifier is supplied,

said amplifier having;

inverters on (2n+1) stages (where n is an integer not less than

     1) which are cascade-connected; and

capacitor elements respectively connected between said (2n+1) stages of said inverters and between an input terminal of said inverter on a first stage and an output terminal of said inverter on a last stage,

each of said inverters on said (2n+1) stages having first and second power supply terminals,

a reference voltage which differs in accordance with each of said inverters on said (2n+1) stages being supplied to at least one of said first and second power supply terminals, a reference voltage which is supplied to at least one of said first and second power supply terminals of each of said inverters from said second stage to said 2n-th stage being not less than a reference voltage supplied to at least one of said first and second power supply terminals of said inverter on said last stage, and a reference voltage supplied to at least one of said first and second power supply terminals of said inverter on said first stage being not more than a reference voltage supplied to at least one of said first and second power supply terminals of said inverter on said second stage.

16. A display apparatus comprising:

signal lines and scanning lines which are vertically and horizontally provided in rows on an insulation substrate;

display elements which is formed in the vicinity of the respective intersections of said signal lines and said scanning lines;

a scanning line drive circuit which drives said scanning lines; and

a signal line drive circuit which is formed on said insulation substrate and drives said signal lines,

said signal line drive circuit having;

an amplifier which amplifies an analog video signal; and

a signal line selection circuit which selects a signal line to which said analog video signal amplified by said amplifier is supplied, and performs signal line writing,

said amplifier having;

a plurality of first amplification portions each of which is constituted by one or more inverters, and which are connected to each other in parallel;

a second amplification portion consisting of a plurality of inverters which are cascade-connected;

a selection portion which sequentially selects any one of a plurality of said first amplification portions, supplies an output of a selected first amplification portion to an inverter on a first stage of said second amplification portion, and feeds back an output of said second amplification portion to an input side of an inverter on a first stage of said selected first amplification portion in order to form a closed loop; and

a plurality of capacitor elements which are respectively connected between stages of respective inverters in said closed loop,

said amplifier amplifying an analog video signal corresponding to a next signal line to which writing is performed while said signal line selection circuit is performing signal line writing.

19. A display apparatus comprising:

signal lines and scanning lines which are vertically and horizontally provided in rows on an insulation substrate;

display elements which are formed in the vicinity of the respective intersections of said signal lines and said scanning lines;

a scanning line drive circuit which drives said scanning lines;

a signal line drive circuit which is formed on said insulation substrate and drives said signal lines; and

a power supply voltage generation circuit which generates a second power supply voltage having a voltage level which is a substantially integral multiple of a first power supply voltage supplied from the outside based on said first power supply voltage,

said signal line drive circuit having;

an amplifier which amplifies an analog video signal; and

a signal line selection circuit which selects a signal line to which said analog video signal amplified by said amplifier is supplied, and performs signal line writing,

said amplifier being driven with said second power supply voltage.

22. A digital-to-analog conversion circuit which outputs a voltage corresponding to a digital signal consisting of n (n is an integer not less than 2) bits based on a first reference voltage and a second reference voltage whose voltage level is lower than that of said first reference voltage, comprising:

a first capacitor element capable of storing an electric charge according to a value of each bit other than a most significant bit in said digital signal;

a second capacitor element capable of redistributing a stored electric charge between itself and said first capacitor element;

a third capacitor element capable of storing an electric charge according to a value of a most significant bit in said digital signal; and

an electric charge control circuit which repeatedly performs in accordance with each bit other than a most significant bit in said digital signal, processing of sequentially storing an electric charge according to a value of each bit other than a most significant bit in said digital signal into said first capacitor element and redistributing a stored electric charge between said first capacitor element and said second capacitor element, stores an electric charge according to a value of a most significant bit in said digital signal into said third capacitor element, and then carries out redistribution of a stored electric charge between said second capacitor element and said third capacitor element.

23. The digital-to-analog conversion circuit according to claim 22, further comprising:

a first switching circuit which switches whether redistribution of a stored electric charge is performed between said first capacitor element and said second capacitor element;

a second switching circuit which switches whether an electric charge according to a value of a most significant bit in said digital signal is stored in said third capacitor element; and

a third switching circuit which switches whether redistribution of a stored electric charge is performed between said second capacitor element and said third capacitor element,

wherein said electric charge control circuit stores an electric charge according to a value of each bit into said first capacitor element in accordance with each bit other than a most significant bit in said digital signal, then turns on said first switching circuit in order to redistribute the stored electric charge between said first capacitor element and said second capacitor element and turns on said second switching circuit in order to store the electric charge in accordance with a value of a most significant bit in said digital signal, and then turns on said third switching circuit in order to redistribute the stored electric charge between said second capacitor element and said third capacitor element.

24. The digital-to-analog conversion circuit according to claim 23, further comprising a fourth switching circuit which switches whether an electric charge according to said second reference voltage is stored in said second capacitor element,

wherein said electric charge control circuit turns on said fourth switching circuit and stores in said second capacitor element an electric charge according to said second reference voltage when storing in said first capacitor element an electric charge according to a least significant bit in said digital signal.

25. The digital-to-analog conversion circuit according to claim 23, further comprising:

an amplifier which supplies a voltage to a load capacitance in a second period in such a manner that a voltage of said load capacitance becomes equal to a voltage according to a stored electric charge of said third capacitor element in a first period; and

a fifth switching circuit which switches whether input and output terminals of said amplifier are short-circuited,

wherein, after storing in said first capacitor element an electric charge according to a value of each bit in accordance with each bit other than a most significant bit in said digital signal, said electric charge control circuit turns on said first switching circuit and performs redistribution of a stored electric charge between said first capacitor element and said second capacitor element, then turns on said second switching circuit and stores in said third capacitor element an electric charge according to a value of a most significant bit in said digital signal, subsequently turns on said third switching circuit and performs redistribution of a stored electric charge between said second capacitor element and said third capacitor element, and turns on said fifth switching circuit and short-circuits input and output terminals of said amplifier in an on period of said second switching circuit and an on period of said third switching circuit.

26. The digital-to-analog conversion circuit according to claim 23, further comprising:

a sixth switching circuit which switches whether an output from said amplifier is supplied to a load; and

a seventh switching circuit which is connected between a connection point of said sixth switching circuit and said load and a connection point of said second switching circuit and said third capacitor element,

wherein said electric charge control circuit turns on said sixth and seventh switching circuits and supplies to said load a voltage at said connection point of said second switching circuit and said third capacitor element except an on period of said second switching circuit and an on period of said third switching circuit.

27. A display apparatus comprising:

a plurality of switching elements which are respectively provided in the vicinity of the respective intersections of a signal lines and a scanning lines;

a signal line drive circuit which drives signal lines; and

a scanning line drive circuit which drives scanning lines,

said signal line drive circuit having said digital-to-analog conversion circuit defined in claim 22 which converts a digital signal indicative of pixel information into an analog signal,

an output from said digital-to-analog conversion circuit being supplied to a corresponding signal line.

28. The display apparatus according to claim 27, further comprising reference voltage selecting means for selecting two types of reference voltages based on a bit string on a upper bit side in a digital signal indicative of image information supplied to said signal line drive circuit,

said first and third capacitor elements storing electric charges according to said two types of reference voltages selected by said reference voltage selecting means.

29. A digital-to-analog conversion method which outputs a voltage which ranges between a first voltage and a second voltage and corresponds to a digital signal consisting of n (n is an integer not less than 2) bits,

wherein said method repeatedly performs in accordance with each bit other than a most significant bit in said digital signal processing of sequentially storing in a first capacitor element an electric charge according to a value of each bit other than a most significant bit in said digital signal and performing redistribution of the stored electric charge between said first capacitor element and a second capacitor element, stores in a third capacitor element an electric charge according to a value of a most significant bit in said digital signal, and then carries out redistribution of a stored electric charge between said second capacitor element and said third capacitor element.