Signal drive circuit, display device, electro-optical device, and signal drive method

• US 20020190973A1
• Filed: 05/23/2002
• Published: 12/19/2002
• Est. Priority Date: 05/24/2001
• Status: Active Grant

• Current Assignee: Seiko Epson Corporation (Seiko Group)
• Original Assignee: Seiko Epson Corporation (Seiko Group)
• Inventors: Morita, Akira
• Granted Patent: US 7,002,568 B2
• Time in Patent Office: Days
• US Class Current: 345/204
• CPC Class Codes: G09G 2310/0232 Special driving of display border areas
• CPC Class Codes: G09G 2310/027 Details of drivers for data electrodes, the drivers handling digital grey scale data, e.g. use of D/A converters
• CPC Class Codes: G09G 2310/0283 Arrangement of drivers for different directions of scanning
• CPC Class Codes: G09G 2310/0289 Details of voltage level shifters arranged for use in a driving circuit
• CPC Class Codes: G09G 2310/0291 Details of output amplifiers or buffers arranged for use in a driving circuit
• CPC Class Codes: G09G 2310/0297 Special arrangements with multiplexing or demultiplexing of display data in the drivers for data electrodes, in a pre-processing circuitry delivering display data to said drivers or in the matrix panel, e.g. multiplexing plural data signals to one D/A converter or demultiplexing the D/A converter output to multiple columns
• CPC Class Codes: G09G 2310/04 Partial updating of the display screen
• CPC Class Codes: G09G 2330/021 Power management, e.g. power saving
• CPC Class Codes: G09G 2340/0414 Vertical resolution change
• CPC Class Codes: G09G 2340/0421 Horizontal resolution change
• CPC Class Codes: G09G 2340/0471 Vertical positioning
• CPC Class Codes: G09G 2340/0478 Horizontal positioning
• CPC Class Codes: G09G 3/3614 Control of polarity reversal in general
• CPC Class Codes: G09G 3/3648 using an active matrix G09G3/367 - G09G3/3696 take precedence
• CPC Class Codes: G09G 3/3666 with the matrix divided into sections
• CPC Class Codes: G09G 3/3677 suitable for active matrices only
• CPC Class Codes: G09G 3/3688 suitable for active matrices only
• CPC Class Codes: G09G 3/3696 Generation of voltages supplied to electrode drivers

Abstract

A signal drive circuit for an active matrix type liquid crystal panel. This signal drive circuit comprises: a shift register for shifting image data sequentially on a block basis, each block constituting a plurality of signal lines, to correspond to signal lines of a block; a line latch for latching the image data in synchronization with a horizontal synchronizing signal; a drive voltage generation circuit for generating drive voltages based on the image data; and a signal line drive circuit. This signal driver controls a partial display based on the partial display data which is designated on a block basis. Each of the signal lines in a block set as a display area is driven based on the image data. Each of the signal lines in a block set as a non-display area is driven by a predetermined non-display level voltage generated by a non-display level voltage supply circuit.

Claims

1. A signal drive circuit for driving a plurality of signal lines of an electro-optical device which includes a plurality of pixels defined by a plurality of scan lines and the signal lines crossing each other, based on image data comprising:

a line latch for latching the image data for a horizontal scan period;

a drive voltage generating section for generating drive voltages of the signal lines based on the image data latched by the line latch;

a signal line drive section for driving the signal lines based on the drive voltages generated by the drive voltage generating section; and

a partial display data holding section for holding partial display data which indicates propriety of output of the drive voltages to the signal lines on a block basis, each block constituting a predetermined number of signal lines,

wherein the signal line drive section controls the output of the drive voltages to the signal lines on a block basis based on the partial display data.

2. The signal drive circuit according to claim 1, further comprising:

a shift register for shifting the sequentially supplied image data to supply the image data to the line latch per horizontal scan unit;

a shift direction switching section for switching shift direction of the shift register based on a predetermined shift direction switching signal; and

a data interchange section for interchanging order of the partial display data which is held in the partial display data holding section on a block basis, based on the predetermined shift direction switching signal,

wherein the signal line drive section controls the output of the drive voltages of the signal lines on a block basis based on the partial display data supplied from the data interchange section.

3. The signal drive circuit according to claim 1,

wherein the signal line drive section includes:

an impedance conversion section for subjecting drive voltages generated by the drive voltage generating section to impedance conversion to output the impedance-converted drive voltages to the signal lines; and

a non-display level voltage supplying section for generating predetermined non-display level voltages on the signal lines, and

wherein each of the signal lines is driven by one of the impedance conversion section and the non-display level voltage supplying section on a block basis based on the partial display data.

4. The signal drive circuit according to claim 3,

wherein the impedance conversion section subjects drive voltages to impedance conversion, outputs the impedance-converted drive voltages to signal lines of a block in which output of the impedance conversion section is turned ON due to the partial display data and sets signal lines of a block in which the output of the impedance conversion section is turned OFF due to the partial display data to a high impedance state, and

wherein the non-display level voltage supplying section sets signal lines of a block in which output of the non-display level voltage supplying section is turned ON due to the partial display data to a high impedance state and supplies predetermined non-display level voltages to signal lines of a block in which the output of the non-display level voltage supplying section is turned OFF due to the partial display data.

5. The signal drive circuit according to claim 1,

wherein the drive voltage generating section interrupts generation of drive voltages for driving signal lines of a block in which output of the drive voltage generating section is turned OFF due to the partial display data.

6. The signal drive circuit according to claim 3,

wherein the electro-optical device includes pixel electrodes corresponding to the respective pixels provided via switching sections connecting the scan lines and the signal lines, and

wherein the non-display level voltage sets a voltage difference between voltages applied to the pixel electrodes and voltages of counter electrodes opposite to the pixel electrodes via electro-optical elements lower than a predetermined threshold value.

7. The signal drive circuit according to claim 3,

wherein the electro-optical device includes pixel electrodes corresponding to the respective pixels provided via switching sections connecting the scan lines and the signal lines, and

wherein the non-display level voltage is substantially equal to voltages on counter electrodes opposite to the pixel electrodes via electro-optical elements.

8. The signal drive circuit according to claim 3,

wherein the non-display level voltage is one of maximum and minimum gradation voltages which is generated based on the image data.

9. The signal drive circuit according to claim 1,

wherein each block corresponds to eight pixels.

10. A display device comprising:

a display panel including a plurality of pixels defined by a plurality of scan lines and a plurality of signal lines crossing each other;

a scan drive circuit for scanning and driving the scan lines; and

a signal drive circuit for driving the signal lines based on image data,

wherein the signal drive circuit includes;

a line latch for latching the image data for a horizontal scan period;

a drive voltage generating section for generating drive voltages of the signal lines based on the image data latched by the line latch,;

a signal line drive section for driving the signal lines based on the drive voltages generated by the drive voltage generating section; and

a partial display data holding section for holding partial display data which indicates propriety of output of the drive voltages to the signal lines on a block basis, each block constituting a predetermined number of signal lines, and

wherein the signal line drive section controls the output of the drive voltages to the signal lines on a block basis based on the partial display data.

11. An electro-optical device comprising:

a plurality of pixels defined by a plurality of scan lines and a plurality of signal lines crossing each other;

a scan drive circuit for scanning and driving the scan lines; and

a signal drive circuit for driving the signal lines based on image data,

wherein the signal drive circuit includes;

a line latch for latching the image data for a horizontal scan period;

a drive voltage generating section for generating drive voltages of the signal lines based on the image data latched by the line latch;

a signal line drive section for driving the signal lines based on the drive voltages generated by the drive voltage generating section; and

a partial display data holding section for holding partial display data which indicates propriety of output of the drive voltages to the signal lines on a block basis, each block constituting a predetermined number of signal lines, and

wherein the signal line drive section controls the output of the drive voltages to the signal lines on a block basis based on the partial display data.

12. A signal drive method for a signal drive circuit driving a plurality of signal lines of an electro-optical device including pixels which are defined by a plurality of scan lines and the signal lines crossing each other, comprising the steps of:

latching the image data for a horizontal scan period;

generating drive voltages for each of the signal lines based on the latched image data; and

holding partial display data which indicates propriety of output of the drive voltages to the signal lines on a block basis, each block constituting a predetermined number of signal lines,

wherein the output of the drive voltages to the signal lines is controlled on a block basis based on the partial display data.