Network system-wide error handling utilizing control bit modification

• US 20020191606A1
• Filed: 05/09/2002
• Published: 12/19/2002
• Est. Priority Date: 05/10/2001
• Status: Abandoned Application

• Current Assignee: Zarlink Semiconductor VN Inc (Microchip Technology Incorporated)
• Original Assignee: Zarlink Semiconductor VN Inc (Microchip Technology Incorporated)
• Inventors: Jin, Jian, Wu, Shaofeng, Niu, Autumn, Lai, Po-Shen, Kuo, Jerry
• Application Number:
  US10/142,022
• Publication Number:
  US 20020191606A1
• Time in Patent Office: Days
• US Class Current: 370/389
• CPC Class Codes: H04L 69/324 in the data link layer [OSI layer 2], e.g. HDLC
• CPC Class Codes: H04L 9/40 Network security protocols

Abstract

A communication interface for processing errors between network devices. The communication interface includes an output interface of a first network device for generating output control information and parity information of output information transmitted therefrom, and an error-handling interface of a second network device, which error-handling interface is in operative communication with the output interface to process the output control information and the parity information of the output information by, checking parity of the parity information of the output information received from the first network device, terminating the output information when an error in the parity is detected, and recovering a boundary of the output information when an error in the output control information is detected.

Claims

1. A communication interface for handling errors between network devices, comprising:

an output interface of a first network device for generating output control information and output parity information carried in output information transmitted therefrom; and

an input error-handling interface of a second network device, which input error-handling interface is in operative communication with the output interface to detect errors in the output information.

2. The interface of claim 1, wherein the parity information is determined based upon data information of the output information and the output control information.

3. The interface of claim 1, wherein the input error-handling interface detects errors in the output information by calculating input parity information of the output information, and comparing the input parity information with the output parity information to determine whether to terminate the output information.

4. The interface of claim 1, wherein the input error-handling interface detects errors in the output information by performing a parity check on the output information, and terminating the output information when a parity error is detected, which terminating occurs by performing at least one of discarding the output information, forwarding an error-free portion of the output information, and forwarding all of the erred output information.

5. The interface of claim 1, wherein the input error-handling interface recovers a boundary of the output information when an error in the output control information is not detected.

6. The interface of claim 1, wherein the input error-handling interface recovers a boundary of the output information by utilizing at least one tag bit to define the length of the output information when an error occurs in the output control information that is not detected.

7. The interface of claim 1, wherein the output control information defines a flow-control message that is routed substantially directly to an input port by bypassing a synchronization buffer of the input error-handling interface.

8. The interface of claim 1, wherein the input error-handling interface includes an internal interface logic operatively connected interstitial to the output interface and an internal input interface of the input error-handling interface such that the internal interface logic generates internal control information from the output control information and output parity information, and passes it to the internal input interface.

9. The interface of claim 8, wherein the internal control information includes at least one more bit than the output control information.

10. The interface of claim 1, wherein the input error-handling interface includes an internal interface logic operatively connected interstitial to the output interface and an internal input interface of the input error-handling interface such that the internal interface logic passes data of the output information unmodified to the internal input interface.

11. The interface of claim 1, wherein the first network device is one of a source distributed switch and a switching fabric device, and the second network device is one of a switching fabric device and a destination distributed switch.

12. The interface of claim 1, wherein the input error-handling interface synchronizes the output information to a system clock.

13. The interface of claim 1, wherein at least one input of each of the first network device and the second network device includes the input error-handling interface.

14. The interface of claim 1, wherein at least one output of each of the first network device and the second network device includes the output interface.

15. The interface of claim 1, wherein the input error-handling interface includes an internal interface logic that always sends at least one message to an internal interface for every internal clock period.

16. The interface of claim 15, wherein the at least one message includes an idle/flow control message when no other message is being transmitted.

17. The interface of claim 1, wherein the input error-handling interface detects an error in the middle of the output information and deletes a last word of the output information by marking a word previous to the last word.

18. The interface of claim 1, wherein the input error-handling interface processes the output information to generate a tag information when a message boundary is detected, which tag information is utilized by a queue of the second network device to recover a boundary of the processed output information when an expected length of the processed output information is different from an actual length of the processed output information.

20. The interface of claim 19, wherein the error-handling interface utilizes at least one tag bit to detect the boundary of the output information.

19. A communication interface for processing errors between network devices, comprising:

an output interface of a first network device for generating output control information and parity information of output information transmitted therefrom; and

an error-handling interface of a second network device, which error-handling interface is in operative communication with the output interface to process the output control information and the parity information of the output information by,

checking parity of the parity information of the output information received from the first network device,

terminating the output information when an error in the parity is detected, and

recovering a boundary of the output information when an error in the output control information is detected.

21. A method of handling errors between network devices, comprising:

providing an output interface of a first network device for generating output control information and output parity information carried in output information transmitted therefrom; and

providing an input error-handling interface of a second network device, which input error-handling interface is in operative communication with the output interface to detect errors in the output information.

22. The method of claim 21, wherein the parity information is determined based upon data information of the output information and the output control information.

23. The method of claim 21, wherein the input error-handling interface detects errors in the output information by calculating input parity information of the output information, and comparing the input parity information with the output parity information to determine whether to terminate the output information.

24. The method of claim 21, wherein the input error-handling interface detects errors in the output information by performing a parity check on the output information, and terminating the output information when a parity error is detected, which terminating occurs by performing at least one of discarding the output information, forwarding an error-free portion of the output information, and forwarding all of the erred output information.

25. The method of claim 21, wherein the input error-handling interface recovers a boundary of the output information when an error in the output control information is not detected.

26. The method of claim 21, wherein the input error-handling interface recovers a boundary of the output information by utilizing at least one tag bit to define the length of the output information when an error occurs in the output control information that is not detected.

27. The method of claim 21, wherein the output control information defines a flow-control message that is routed substantially directly to an input port by bypassing a synchronization buffer of the input error-handling interface.

28. The method of claim 21, wherein the input error-handling interface includes an internal interface logic operatively connected interstitial to the output interface and an internal input interface of the input error-handling interface such that the internal interface logic generates internal control information from the output control information and output parity information, and passes it to the internal input interface.

29. The method of claim 28, wherein the internal control information includes at least one more bit than the output control information.

30. The method of claim 21, wherein the input error-handling interface includes an internal interface logic operatively connected interstitial to the output interface and an internal input interface of the input error-handling interface such that the internal interface logic passes data of the output information unmodified to the internal input interface.

31. The method of claim 21, wherein the first network device is one of a source distributed switch and a switching fabric device, and the second network device is one of a switching fabric device and a destination distributed switch.

32. The method of claim 21, wherein the input error-handling interface synchronizes the output information to a system clock.

33. The method of claim 21, wherein at least one input of each of the first network device and the second network device includes the input error-handling interface.

34. The method of claim 21, wherein at least one output of each of the first network device and the second network device includes the output interface.

35. The method of claim 21, wherein the input error-handling interface includes an internal interface logic that always sends at least one message to an internal interface for every internal clock period.

36. The method of claim 35, wherein the at least one message includes an idle/flow control message when no other message is being transmitted.

37. The method of claim 21, wherein the input error-handling interface detects an error in the middle of the output information and deletes a last word of the output information by marking a word previous to the last word.

38. The method of claim 21, wherein the input error-handling interface processes the output information to generate tag information when a message boundary is detected, which tag information is utilized by a queue of the second network device to recover a boundary of the processed output information when an expected length of the processed output information is different from an actual length of the processed output information.

40. The method of claim 39, wherein the input error-handling interface in the step of receiving detects errors in the input information by performing the steps of:

checking parity on the input information to detect the erred information; and

terminating the erred input information by performing one of discarding the erred information, forwarding an error-free portion of the erred information, and forwarding all of the erred information.

41. The method of claim 39, wherein the input error-handling interface recovers a boundary of the input information by utilizing at least one tag bit to define a length of the input information when an error in input control information of the input information is not detected.

42. The method of claim 39, wherein the input information includes input control information that defines a flow control message, which flow control message is routed substantially directly to a device input port by bypassing a synchronization buffer of the input error-handling interface.

43. The method of claim 39, wherein the network device is one of a distributed switch and a switching fabric.

44. The method of claim 39, wherein the input error-handling interface includes an internal interface logic that always sends at least one message to an internal interface for every internal clock period, which at least one message is an idle/flow control message when no other message is being transmitted.

45. The method of claim 39, wherein the input error-handling interface processes the input information to generate processed input information, which processed input information includes tag information associated with a message boundary, and which tag information is utilized by a queue of the network device to recover a boundary of the processed input information when an expected length of the processed input information is different from an actual length of the processed input information.

46. The method of claim 39, wherein the input error-handling interface includes an internal interface logic operatively connected interstitial to the input port and an internal input interface of the input error-handling interface, such that the internal interface logic generates internal control information from the input information and passes the internal control information to the internal input interface.

47. The method of claim 39, wherein the input error-handling interface detects an error in the middle of the erred information and deletes a last word of the erred information by marking a word previous to the last word.

48. The method of claim 39, wherein the input error-handling interface detects the erred information by calculating input parity information of the input information, and comparing the input parity information with transmitted parity information of the input information.

50. The method of claim 49, wherein the input error-handling interface recovers a boundary of the input information by utilizing at least one tag bit to define a length of the input information when an error in input control information of the input information is not detected.

39. A method of handling errors in a network device, comprising the steps of:

receiving input information of an input port with an input error-handling interface of the network device;

processing the input information with the input error-handling interface to detect erred information and error-free information; and

transmitting with an output interface output information that includes the error-free information, output control information, and parity information.

49. A method of handling errors in a network device, comprising the steps of:

receiving input information of an input port with an input error-handling interface of the network device;

checking parity on the input information with the input error-handling interface to detect erred information and error-free information;

terminating the erred information by performing one of discarding the erred information, forwarding an error-free portion of the erred information, and forwarding all of the erred information;

transmitting with an output interface output information that includes the error-free information, output control information, and parity information.