Digital phase locked loop
First Claim
1. A phase locked loop circuit, comprising:
- a controllable oscillator for generating an output signal of desired frequency;
a first phase detection circuit for generating an output indicative of phase differential responsive to said output signal and a first edge of a reference signal;
a second phase detection circuit for generating an output indicative of phase differential responsive to said output signal and a second edge of a reference signal; and
circuitry for controlling said controllable oscillator responsive to said outputs of said first and second phase detections circuits.
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Accused Products
Abstract
A phase locked loop circuit (30, 100, 110) includes a controllable oscillator (42) for generating an output signal of desired frequency responsive to a control signal, a first phase detection circuit (32, 102, 112) for generating an output indicative of phase differential responsive to the output signal and a first edge of a reference signal and a second phase detection circuit (34, 104, 114) for generating an output indicative of phase differential responsive to the output signal and a second edge of a reference signal. The control signal to the controllable oscillator (42) is driven by the outputs of the first and second phase detections circuits.
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Citations
32 Claims
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1. A phase locked loop circuit, comprising:
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a controllable oscillator for generating an output signal of desired frequency;
a first phase detection circuit for generating an output indicative of phase differential responsive to said output signal and a first edge of a reference signal;
a second phase detection circuit for generating an output indicative of phase differential responsive to said output signal and a second edge of a reference signal; and
circuitry for controlling said controllable oscillator responsive to said outputs of said first and second phase detections circuits. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A method of synthesizing a frequency in a phase locked loop circuit, comprising:
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generating a first phase differential output responsive to said output signal and a first edge of a reference signal;
generating a second phase differential output responsive to said output signal and a second edge of a reference signal; and
controlling a controllable oscillator responsive to said outputs of said first and second phase detections circuits. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16, 18, 19, 20, 21, 22, 23, 24, 26, 27, 28, 29, 30, 31, 32)
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17. A mobile communications device comprising:
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a frequency synthesizer for generating a carrier frequency output responsive to a local reference clock;
circuitry for generating multiple clock signals of different frequencies synchronous to said carrier frequency output;
digital baseband circuitry operating responsive to one or more of said multiple clock signals.
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25. A method of processing mobile communications, comprising the steps of:
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generating a carrier frequency output responsive to a local reference clock;
generating multiple clock signals of different frequencies synchronous to said carrier frequency output;
operating digital baseband circuitry responsive to one or more of said multiple clock signals.
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Specification