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Digital phase locked loop

  • US 20020191727A1
  • Filed: 04/24/2002
  • Published: 12/19/2002
  • Est. Priority Date: 04/25/2001
  • Status: Active Grant
First Claim
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1. A phase locked loop circuit, comprising:

  • a controllable oscillator for generating an output signal of desired frequency;

    a first phase detection circuit for generating an output indicative of phase differential responsive to said output signal and a first edge of a reference signal;

    a second phase detection circuit for generating an output indicative of phase differential responsive to said output signal and a second edge of a reference signal; and

    circuitry for controlling said controllable oscillator responsive to said outputs of said first and second phase detections circuits.

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