Digital phase locked loop

• US 20020191727A1
• Filed: 04/24/2002
• Published: 12/19/2002
• Est. Priority Date: 04/25/2001
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Leipold, Dirk, Staszewski, Robert B.
• Granted Patent: US 8,385,476 B2
• Time in Patent Office: Days
• US Class Current: 375/376
• CPC Class Codes: H03C 3/0966 modulating the reference clock
• CPC Class Codes: H03K 19/0016 by using a control or a clock signal, e.g. in order to apply power supply
• CPC Class Codes: H03L 2207/50 All digital phase-locked loop
• CPC Class Codes: H03L 7/08 Details of the phase-locked loop
• CPC Class Codes: H03L 7/085 concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal H03L7/10 takes precedence; circuits for comparing the phase or frequency of two mutually-independent oscillations H03D13/00
• CPC Class Codes: H03L 7/087 using at least two phase detectors or a frequency and phase detector in the loop
• CPC Class Codes: H03L 7/091 the phase or frequency detector using a sampling device H03L7/087 takes precedence
• CPC Class Codes: H03L 7/093 using special filtering or amplification characteristics in the loop H03L7/087 - H03L7/091 take precedence
• CPC Class Codes: H03L 7/099 concerning mainly the controlled oscillator of the loop
• CPC Class Codes: H03L 7/0991 the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider H03L7/0995 takes precedence; fixed oscillators with means for selecting among various phases H03L7/0814
• CPC Class Codes: H03L 7/0992 comprising a counter or a frequency divider
• CPC Class Codes: H03L 7/16 Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
• CPC Class Codes: H04L 7/0029 interpolation of received data signal
• CPC Class Codes: H04L 7/0331 with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock H04L7/0337 takes precedence

Abstract

A phase locked loop circuit (30, 100, 110) includes a controllable oscillator (42) for generating an output signal of desired frequency responsive to a control signal, a first phase detection circuit (32, 102, 112) for generating an output indicative of phase differential responsive to the output signal and a first edge of a reference signal and a second phase detection circuit (34, 104, 114) for generating an output indicative of phase differential responsive to the output signal and a second edge of a reference signal. The control signal to the controllable oscillator (42) is driven by the outputs of the first and second phase detections circuits.

Claims

1. A phase locked loop circuit, comprising:

a controllable oscillator for generating an output signal of desired frequency;

a first phase detection circuit for generating an output indicative of phase differential responsive to said output signal and a first edge of a reference signal;

a second phase detection circuit for generating an output indicative of phase differential responsive to said output signal and a second edge of a reference signal; and

circuitry for controlling said controllable oscillator responsive to said outputs of said first and second phase detections circuits.

2. The phase locked loop circuit of claim 1 and further comprising circuitry for adjusting the output of said second phase detection circuit to account for a variation of said reference signal from a 50% duty cycle.

3. The phase locked loop circuit of claim 1 wherein said outputs of said first and second phase detection circuits are added on each edge of said reference signal.

4. The phase locked loop circuit of claim 1 wherein said outputs of said first and second phase detection circuits are added on a predetermined edge of said reference signal.

5. The phase locked loop circuit of claim 1 wherein said first detection circuit generates an output responsive to the output signal and a rising edge of said reference signal and said second detection circuit generates an output responsive to the output signal and a falling edge of said reference signal.

6. The phase locked loop circuit of claim 1 wherein said first detection circuit generates an output responsive to the output signal and a falling edge of said reference signal and said second detection circuit generates an output responsive to the output signal and a rising edge of said reference signal.

7. The phase locked loop circuit of claim 1 wherein said first and second phase detection circuits comprise a time-to-digital converter for generating a digital value indicative of said phase differential.

8. The phase locked loop circuit of claim 7 wherein said digital value has a fractional part and an integer part.

9. A method of synthesizing a frequency in a phase locked loop circuit, comprising:

generating a first phase differential output responsive to said output signal and a first edge of a reference signal;

generating a second phase differential output responsive to said output signal and a second edge of a reference signal; and

controlling a controllable oscillator responsive to said outputs of said first and second phase detections circuits.

10. The phase locked loop circuit of claim 9 and further comprising circuitry for adjusting the output of said second phase detection circuit to account for a variation of said reference signal from a 50% duty cycle.

11. The phase locked loop circuit of claim 9 wherein said outputs of said first and second phase detection circuits are added on each edge of said reference signal.

12. The phase locked loop circuit of claim 9 wherein said outputs of said first and second phase detection circuits are added on a predetermined edge of said reference signal.

13. The phase locked loop circuit of claim 9 wherein said first detection circuit generates an output responsive to the output signal and a rising edge of said reference signal and said second detection circuit generates an output responsive to the output signal and a falling edge of said reference signal.

14. The phase locked loop circuit of claim 9 wherein said first detection circuit generates an output responsive to the output signal and a falling edge of said reference signal and said second detection circuit generates an output responsive to the output signal and a rising edge of said reference signal.

15. The phase locked loop circuit of claim 9 wherein said first and second phase detection circuits comprise a time-to-digital converter for generating a digital value indicative of said phase differential.

16. The phase locked loop circuit of claim 15 wherein said digital value has a fractional part and an integer part.

18. The mobile communications device of claim 17 and further comprising circuitry for synchronizing said carrier frequency output to an external master clock.

19. The mobile communications device of claim 18 wherein said local reference clock runs independently of said master clock.

20. The mobile communications device of claim 17 wherein said frequency synthesizer includes one or more phase detectors that perform timing updates with said local reference clock responsive to one of said multiple clock signals.

21. The mobile communications device of claim 20 wherein said one or more phase detectors provide information on phase differential between said local reference clock and one of said multiple clocks to said digital baseband circuit.

22. The mobile communications device of claim 17 wherein said circuitry for generating multiple clock signals comprises one or more frequency divider circuits.

23. The mobile communications device of claim 22 wherein said frequency divider circuits are dynamically programmable with a divisor.

24. The mobile communications device of claim 17 wherein said digital baseband circuitry outputs symbols and further comprising circuitry for generating sample points for said symbols responsive to one of said multiple clocks.

26. The method of claim 25 and further comprising the step of synchronizing said carrier frequency output to an external master clock.

27. The method of claim 26 and further comprising the step of generating the local reference clock independently of said master clock.

28. The method of claim 25 wherein said step of generating a carrier frequency comprises the step of performing timing updates with said local reference clock responsive to one or more phase detectors coupled to one of said multiple clock signals.

29. The method of claim 28 and further comprising the step of communicating information on phase differential between said local reference clock and one of said multiple clocks from said one or more phase detectors to said digital baseband circuit.

30. The method of claim 25 wherein said step of generating multiple clock signals comprises the step of dividing said carrier frequency output using one or more frequency divider circuits.

31. The method of claim 30 wherein said dividing step includes the step of dynamically changing a divisor in a frequency divider circuits.

32. The method of claim 25 wherein said digital baseband circuitry outputs symbols and further comprising step of generating sample points for said symbols responsive to one of said multiple clocks.

17. A mobile communications device comprising:

a frequency synthesizer for generating a carrier frequency output responsive to a local reference clock;

circuitry for generating multiple clock signals of different frequencies synchronous to said carrier frequency output;

digital baseband circuitry operating responsive to one or more of said multiple clock signals.

25. A method of processing mobile communications, comprising the steps of:

generating a carrier frequency output responsive to a local reference clock;

generating multiple clock signals of different frequencies synchronous to said carrier frequency output;

operating digital baseband circuitry responsive to one or more of said multiple clock signals.