Semiconductor device having LDD-type source/drain regions and fabrication method thereof

• US 20020192868A1
• Filed: 06/14/2002
• Published: 12/19/2002
• Est. Priority Date: 06/14/2001
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kim, Do-Hyung
• Granted Patent: US 6,737,308 B2
• Time in Patent Office: Days
• US Class Current: 438/112
• CPC Class Codes: H01L 21/28247 passivation or protection of the electrode, e.g. using re-oxidation
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 21/823425 manufacturing common source or drain regions between a plurality of conductor-insulator-semiconductor structures
• CPC Class Codes: H01L 21/823468 with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823864 with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/6653 using the removal of at least part of spacer, e.g. disposable spacer
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET

Abstract

A semiconductor device comprising LDD-type source/drain regions. A gate pattern is formed in insulated relationship over a substrate. Low-concentration implant regions may be formed in a surface layer of the substrate on both sides of the gate pattern. A second spacer layer may be formed conformal to a surface of the substrate and gate pattern. A first spacer may be formed on the second spacer layer and along the sidewalls of the gate pattern. A high-concentration implant may then be formed within the low-concentration source/drain regions using the gate pattern and the first spacer as ion-implantation masks. Thereafter, the first spacer is removed. Second spacers may then be formed from the second spacer layer and metal silicide patterned within exposed surface areas of the substrate as defined by the second spacers. An interlayer insulation layer may then be formed over the substrate and patterned to form contact holes to source/drain regions between the gate patterns.

Claims

1. A method of fabricating a semiconductor to provide LDD-type source/drain regions, comprising:

forming at least one gate pattern in insulated relationship over a semiconductor substrate;

implanting low-concentration impurity ions to form source/drain regions within the semiconductor substrate on both sides of the gate pattern;

forming a second spacer layer conformal to the surface of the semiconductor substrate and the gate pattern, the second spacer to extend over the source/drain regions;

forming a first spacer on the second spacer layer and along the sidewalls of the gate pattern;

forming a high-concentration implant regions into the source/drain regions using at least the gate pattern and the first spacer as ion-implantation masks;

removing the first spacer;

anisotropically etching the second spacer layer to expose portions of at least source/drain regions and to concurrently form second spacers on sidewalls of the gate pattern; and

stacking and thermally treating a metal over the exposed portions of substrate as defined by the second spacers.

2. A method according to claim 1, which the thermally treating comprises forming a metal silicide where the metal contacts the source/drain regions.

3. The method of claim 2, further comprising:

stacking an etch stop layer over the substrate; and

stacking an interlayer insulation over the etch stop layer, wherein the interlayer insulating layer has an etch selectivity with respect to the etch stop layer.

4. The method of claim 3, in which the etch stop layer is formed of a silicon oxynitride (SiON).

5. The method of claim 3, in which the second spacer layer is formed of a material allowing selectable etching of the interlayer insulation layer and the first spacer relative thereto.

6. The method of claim 2, further comprising, after forming the second spacer and before forming the metal suicide layer, implanting impurity ions of medium concentration.

7. A semiconductor device comprising:

at least one MOS transistor having a gate pattern insulated from a substrate by a gate insulation layer;

spacers along sidewalls of the gate pattern;

LDD-type source/drain regions within the substrate at locations beside the gate pattern; and

metal silicide within a surface layer of the substrate at locations thereof defined by the spacers;

the LDD-type source/drain regions comprising;

a low-concentration impurity implant region within surface regions of the substrate at locations internally beyond sidewalls of the gate pattern; and

a high-concentration impurity implant region within surface regions of the substrate at locations spaced internally beyond the edge of the spacers along the sidewalls of the gate pattern.

8. The semiconductor device of claim 7, further comprising;

a capping layer over the gate pattern.

9. The semiconductor device of claim 8, in which the capping layer comprises material the same as the spacer.

10. The semiconductor device of claim 7, further comprising metal silicide within a surface layer of polysilicon of the gate pattern.

11. The semiconductor device of claim 7, in which the LDD-type source/drain regions have a three-step impurity implant structure comprising a medium-concentration impurity implant region formed at regions of the substrate laterally outward from edges of the spacers along the sidewalls of the gate pattern.

12. The semiconductor device of claim 11, in which the metal silicide layer is formed with a surface layer region of the substrate substantially aligned with the medium-concentration impurity implant region and the high-concentration impurity implant region.

13. The semiconductor device of claim 7, further comprising an etch stop layer between the gate pattern and the interlayer insulation layer.

14. The semiconductor device of claim 13, in which the etch stop layer comprises material allowing selective etching of the interlayer relative thereto.

15. The semiconductor device of claim 13, in which the etch stop layer is thinner than the distance between the outside of the spacer and the boundary of the highconcentration impurity implant region.