Low latency inter-reference ordering in a multiple processor system employing a multiple-level inter-node switch

• US 20020194290A1
• Filed: 04/26/2001
• Published: 12/19/2002
• Est. Priority Date: 04/26/2001
• Status: Active Grant

• Current Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Original Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Inventors: Steely, Simon C. Jr., Van Doren, Stephen R., Sharma, Madhumitra
• Granted Patent: US 6,904,465 B2
• Time in Patent Office: Days
• US Class Current: 709/213
• CPC Class Codes: G06F 15/17393 having multistage networks, e.g. broadcasting scattering, gathering, hot spot contention, combining/decombining
• CPC Class Codes: H04L 49/102 using shared medium, e.g. bus or ring
• CPC Class Codes: H04L 49/15 Interconnection of switching modules

Abstract

A multiple-processor system in which a commit message is returned to a source processor that requests a memory access operation so as to indicate the apparent completion of the operation includes a multiple-level switch unit linking nodes that contain the processors. The switch unit includes multiple input switches each of which receives messages from multiple nodes, and a set of output switches whose inputs are the outputs of the input switches and whose outputs are the inputs of the nodes. Each switch processes messages in the order in which they are received by the switch and each output switch follows the same rule as the other output switches.

Claims

1. A multiple-processor system comprising:

a) A plurality of nodes, each node including one or more processors, a shared memory space, portions of which are resident in respective nodes;

b) an inter-node switch unit linking each of the nodes with other nodes to provide the communication among the nodes, the switch unit serving as an ordinary point for memory reference requests;

said switch unit comprising;

1. a plurality of input switches, each of which (a) is connected to receive messages transmitted by a different group of processors;

(b) and is configured to transmit messages selectively over a plurality of inter-switch output terminals, and (c) issues atomic messages corresponding to each memory reference request from a node connected to that switch;

2. a plurality of output switches, each of which;

a) is connected to receive messages from an inter-switch output terminal of each of the input switches and,

b) selectively transmits outputs to a group of nodes connected to that switch; and

c) follows the same ordering rule relative to input switches from which the messages are received simultaneously.

2. The system defined in claim 1 in which all of said input switches operate in synchronism with the same clock.

3. The system defined in claim 1 in which all of said output switches operate in synchronism with the same clock.

4. The system defined in claim 1 in which

A. a source node containing a processor that issues a memory write request transmits the request to a home node of the memory location involved in the re quest;

B. the home node transmits to the input switch connected thereto a message packet identifying (1) the memory location, (2), the processors having copies of contents of the memory location and (3) the processor that is the source of the request; and

C. The input switch transmits (1) messages identifying the memory location to he processors identified in the message from the home node, and (2) acknowledgement message to the home node, the messages from the switch to the source node and the home node being transmitted no earlier than any of the other messages.