Programmable interface controller suitable for spanning clock domains

• US 20020194519A1
• Filed: 05/08/2001
• Published: 12/19/2002
• Est. Priority Date: 05/08/2001
• Status: Active Grant

• Current Assignee: Globespan Virata, Inc., Intersil Americas LLC (Renesas Electronics Corporation), Conexant Incorporated (Synaptics Incorporated)
• Original Assignee: Conexant Incorporated (Synaptics Incorporated)
• Inventors: Fischer, Michael Andrew
• Granted Patent: US 6,807,640 B2
• Time in Patent Office: Days
• US Class Current: 713/600
• CPC Class Codes: G06F 13/4059 where the synchronisation uses buffers, e.g. for speed matching between buses
• CPC Class Codes: H04J 3/02 Details electronic switching or gating H03K17/00
• CPC Class Codes: H04L 7/005 Correction by an elastic buffer
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A programmable interface controller for transmitting data to an output device that is suitable in both fully synchronous systems and in systems that span clock domains. The illustrative embodiments comprise: receiving a plurality of field identifiers and an indication of an order by which each of the plurality of field identifiers is to be uniquely associated with each field in a sequence of fields; receiving a stream of data that comprises the sequence of fields and an indication of the boundary between successive fields in the sequence of fields; and processing each field in the stream of data in accordance with the field identifier uniquely associated with that field.

Claims

1. A method comprising:

receiving a plurality of field identifiers and an indication of an order by which each of said plurality of field identifiers is to be uniquely associated with each field in a sequence of fields;

receiving a stream of data that comprises said sequence of fields and an indication of the boundary between successive fields in said sequence of fields; and

processing each field in said stream of data in accordance with said field identifier uniquely associated with that field.

2. The method of claim 1 wherein said indication of said order by which each of said plurality of field identifiers is to be uniquely associated with each field in said sequence of fields is implicitly indicated by the manner in which said plurality of field identifiers is received.

3. The method of claim 1 wherein said indication of said order by which each of said plurality of field identifiers is to be uniquely associated with each field in said sequence of fields is explicitly indicated.

4. The method of claim 1 wherein said sequence of fields is interlaced with said indication of the boundary between successive fields in said sequence of fields.

5. The method of claim 1 wherein said reception of said plurality of field identifiers occurs before said reception of said stream of data.

6. The method of claim 1 wherein one of said field identifiers occurs more than once in said plurality of field identifiers.

7. An apparatus comprising:

a memory for storing a plurality of field identifiers and an indication of an order by which each of said plurality of field identifiers is to be uniquely associated with each field in a sequence of fields; and

a processor for receiving a stream of data that comprises said sequence of fields and an indication of the boundary between successive fields in said sequence of fields, and for processing each field in said stream of data in accordance with said field identifier uniquely associated with that field.

8. The apparatus of claim 7 wherein said indication of said order by which each of said plurality of field identifiers is to be uniquely associated with each field in said sequence of fields is implicitly indicated by the manner in which said plurality of field identifiers is stored.

9. The apparatus of claim 7 wherein said indication of said order by which each of said plurality of field identifiers is to be uniquely associated with each field in said sequence of fields is explicitly indicated.

10. The apparatus of claim 7 wherein said sequence of fields is interlaced with said indication of the boundary between successive fields in said sequence of fields.

11. The apparatus of claim 7 wherein said reception of said plurality of field identifiers occurs before said reception of said stream of data.

12. The apparatus of claim 7 wherein one of said field identifiers occurs more than once in said plurality of field identifiers.

14. The method of claim 13 wherein said output device is a network interface.

15. The method of claim 13 wherein at least a portion of said second stream of output data is unmodified by said adjunct processor.

16. The method of claim 13 wherein said sequence of fields is interlaced with said indication of the boundary between successive fields in said sequence of fields.

17. The method of claim 13 wherein said reception of said plurality of field identifiers occurs before said reception of said stream of data.

18. The method of claim 13 wherein at least one of said field identifiers occurs more than once in said plurality of field identifiers.

19. The method of claim 13 wherein said source processor operates in accordance with a first clock, said adjunct processor operates in accordance with a second clock, and said first clock is different than said second clock.

20. The method of claim 13 wherein said adjunct processor and said source processor both operate in accordance with a first clock.

13. A method comprising:

receiving at an adjunct processor a sequence of field identifiers from a source processor, wherein said sequence of field identifiers implicitly indicates an order by which each of said plurality of field identifiers is to be uniquely associated with each field in a sequence of fields;

receiving at said adjunct processor a first stream of data from said source processor, wherein said first stream of data comprises said sequence of fields and an indication of the boundary between successive fields in said sequence of fields; and

processing at said adjunct processor each field in said first stream of data in accordance with said field identifier uniquely associated with that field to create a second stream of data; and

transmitting said second stream of data to an output device.

21. An integrated circuit comprising:

a source processor for transmitting a plurality of field identifiers and an indication of an order by which each of said plurality of field identifiers is to be uniquely associated with each field in a sequence of fields, and for transmitting a first stream of data that comprises said sequence of fields and an indication of the boundary between successive fields in said sequence of fields;

an adjunct memory; and

a adjunct processor for receiving said plurality of field identifiers and said indication of said order by which each of said plurality of field identifiers is to be uniquely associated with each field in said sequence of fields, for storing said plurality of field identifiers and said indication of said order by which each of said plurality of field identifiers is to be uniquely associated with each field in said sequence of fields into said adjunct memory, for receiving said first stream of data, and for processing each field in said first stream of data in accordance with said field identifier uniquely associated with that field to create a second stream of data.

22. The integrated circuit of claim 21 wherein said output device is a network interface.

23. The integrated circuit of claim 21 wherein at least a portion of said second stream of output data is unmodified by said adjunct processor.

24. The integrated circuit of claim 21 wherein said sequence of fields is interlaced with said indication of the boundary between successive fields in said sequence of fields.

25. The integrated circuit of claim 21 wherein said reception of said plurality of field identifiers occurs before said reception of said stream of data.

26. The integrated circuit of claim 21 wherein at least one of said field identifiers occurs more than once in said plurality of field identifiers.

27. The integrated circuit of claim 21 further comprising an asynchronous buffer between said source processor and said second buffer for carrying said first stream of data from said source processor to said adjunct processor.

28. The integrated circuit of claim 21 wherein said source processor operates in accordance with a first clock, said adjunct processor operates in accordance with a second clock, and said first clock is different than said second clock.

29. The integrated circuit of claim 21 wherein said source processor and said adjunct processor both operate in accordance with a first clock.