Semiconductor integrated circuit and method for manufacturing the same

• US 20020195623A1
• Filed: 08/12/2002
• Published: 12/26/2002
• Est. Priority Date: 07/06/1998
• Status: Active Grant

• Current Assignee: Masatada Horiuchi
• Original Assignee: Masatada Horiuchi
• Inventors: Horiuchi, Masatada
• Granted Patent: US 6,646,296 B2
• Time in Patent Office: Days
• US Class Current: 257/200
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688

Abstract

A semiconductor integrated circuit according to the present invention comprises a MOS transistor formed on an SOI substrate and a subsidiary transistor provided between a body node and a drain node of the MOS transistor and sharing a gate electrode with the MOS transistor, whereby body potential of the MOS transistor is controlled by gate and drain potentials. Accumulated body charge in a non-conducting state in the semiconductor integrated circuit is extracted by a resistor formed between the body node and a source, whereby various phenomena caused by floating body effect are eliminated. Since the body potential of the MOS transistor can be varied without creating an undesirable leakage current path, and hence without limitations to supplied voltage, its threshold voltage can be made variable so as to follow change in an input signal, thereby making it possible to achieve higher speed and lower voltage operation of the semiconductor integrated circuit. According to the present invention, it is possible to eliminate floating body effect, which is the greatest problem with an SOI transistor formed on an SOI substrate, and also to achieve lower voltage and greater current operation of a transistor without posing limitations to supplied voltage and without causing the problem of leakage current.

Claims

1. A semiconductor integrated circuit comprising:

a first MOS field effect transistor of a first conduction type and a second MOS field effect transistor of the first conduction type which form a single unit semiconductor device; and

a device substrate mounted with said single unit semiconductor device and isolated from other semiconductor devices;

wherein a circuit configuration is formed by a semiconductor device group including at least said single unit semiconductor device, said second MOS field effect transistor including a gate electrode connected to a gate electrode of said first MOS field effect transistor;

a drain connected to a drain of said first MOS field effect transistor; and

a source connected to a source of said first MOS field effect transistor via a resistor and a device substrate of said first MOS field effect transistor.

5. A semiconductor integrated circuit as claimed in claim 1,

wherein said semiconductor device is isolated from a supporting substrate of the semiconductor integrated circuit by an insulator, and is isolated from another semiconductor device by an insulator.

28. A semiconductor integrated circuit as claimed in any one of claims 1, 2, 5, 6, 9, 10, 13, 14, 17, 18, 21, 22, and 26,

wherein said resistor is formed in a semiconductor thin film.

30. A semiconductor integrated circuit as claimed in any one of claims 1, 2, 5, 6, 9, 10, 13, 14, 17, 18, 21, 22, and 26,

wherein said resistor has a resistance value of 500 kΩ

or less and 1 kΩ

or more.

31. A semiconductor integrated circuit as claimed in claims 1, 5, 17, and 21,

wherein an absolute value of threshold voltage of said second transistor is set lower than an absolute value of threshold voltage of said first transistor.

35. A semiconductor integrated circuit as claimed in claims 1, 5, 17, and 21,

wherein channel width of said second transistor is ⅕

or less of channel width of said first transistor.

43. A semiconductor integrated circuit as claimed in any one of claims 1 to 38,

wherein the semiconductor integrated circuit forms an asynchronous transfer mode system.

44. A semiconductor integrated circuit as claimed in any one of claims 1 to 38, 41, and 42,

wherein the semiconductor integrated circuit forms a processor unit.

45. A semiconductor integrated circuit as claimed in any one of claims 1, 2, 5, 6, 17, 21, and 26,

wherein said resistor is formed by a resistive functional device having linear or nonlinear properties, and a resistance value of said resistor is set higher than on resistance of the first transistor.

48. A semiconductor integrated circuit as claimed in claim 47,

wherein a product of CG and RS is equal to or greater than a reciprocal number of an operating frequency.

2. A semiconductor integrated circuit comprising:

a MOS field effect transistor and a capacitor which form a single unit semiconductor device; and

a device substrate mounted with said single unit semiconductor device and isolated from other semiconductor devices;

wherein a circuit configuration is formed by a semiconductor device group including at least said single unit semiconductor device, said capacitor including one electrode connected to a gate electrode of said MOS field effect transistor; and

another electrode connected to a source of said MOS field effect transistor via a resistor and a device substrate of said MOS field effect transistor.

6. A semiconductor integrated circuit as claimed in claim 2,

wherein said semiconductor device is isolated from a supporting substrate of the semiconductor integrated circuit by an insulator, and is isolated from another semiconductor device by an insulator.

18. A semiconductor integrated circuit as claimed in claim 2 or 6,

wherein a plurality of semiconductor devices are connected in series with each other to form a series connection, one end of said series connection being connected to an output node and another end of said series connection being connected to a power supply node, whereby a portion of a NAND type gate circuit or a NOR type gate circuit is formed.

3. A semiconductor integrated circuit comprising:

a first MOS field effect transistor of a first conduction type, a second MOS field effect transistor of the first conduction type, and a third MOS field effect transistor of a second conduction type which form a single unit semiconductor device; and

a device substrate mounted with said single unit semiconductor device and isolated from other semiconductor devices;

wherein a circuit configuration is formed by a semiconductor device group including at least said single unit semiconductor device, said second MOS field effect transistor including a gate electrode connected to a gate electrode of said first MOS field effect transistor; and

a drain connected to a device substrate of said first MOS field effect transistor; and

said third MOS field effect transistor including a gate electrode connected to a gate electrode of said second MOS field effect transistor;

a drain connected to a device substrate of said first MOS field effect transistor; and

a source connected to a source of said first MOS field effect transistor.

4. A semiconductor integrated circuit as claimed in claim 3,

wherein said third MOS field effect transistor is of the first conduction type;

and

the gate electrode of said third transistor is connected to a drain of said first MOS field effect transistor.

7. A semiconductor integrated circuit as claimed in claim 3,

wherein said semiconductor device is isolated from a supporting substrate of the semiconductor integrated circuit by an insulator, and is isolated from another semiconductor device by an insulator.

8. A semiconductor integrated circuit as claimed in claim 4,

wherein said semiconductor device is isolated from a supporting substrate of the semiconductor integrated circuit by an insulator, and is isolated from another semiconductor device by an insulator.

9. A semiconductor integrated circuit comprising:

a supporting substrate having at least a first substrate region and a second substrate region electrically isolated from each other;

a first MOS field effect transistor and a second MOS field effect transistor which form said first substrate region; and

a third MOS field effect transistor and a fourth MOS field effect transistor which form said second substrate region;

wherein a single unit semiconductor device is formed by at least said first to fourth MOS field effect transistors; and

a circuit configuration is formed by a semiconductor device group including at least said single unit semiconductor device, said second MOS field effect transistor including a gate electrode connected to a gate electrode of said first MOS field effect transistor;

a drain connected to a drain of said first MOS field effect transistor; and

a source connected to a source of said first MOS field effect transistor via a first resistor and a device substrate of said first MOS field effect transistor; and

said fourth MOS field effect transistor including a gate electrode connected to a gate electrode of said third MOS field effect transistor;

a drain connected to a drain of said third MOS field effect transistor; and

a source connected to a source of said third MOS field effect transistor via a second resistor and a device substrate of said third MOS field effect transistor.

13. A semiconductor integrated circuit as claimed in claim 9,

wherein said semiconductor device is isolated from the supporting substrate of the semiconductor integrated circuit by an insulator, and is isolated from another semiconductor device by an insulator.

29. A semiconductor integrated circuit as claimed in any one of claims 5, 6, 13, 14, 21, 22, and 26,

wherein said resistor is formed in a single crystalline semiconductor layer in which a transistor is formed.

33. A semiconductor integrated circuit as claimed in claims 9 and 13,

wherein absolute values of threshold voltages of said second transistor and said fourth transistor are set lower than absolute values of threshold voltages of said first transistor and said third transistor.

37. A semiconductor integrated circuit as claimed in claims 9 and 13,

wherein channel widths of said second transistor and said fourth transistor are ⅕

or less of channel widths of said first transistor and said third transistor.

10. A semiconductor integrated circuit comprising:

a supporting substrate having at least a first substrate region and a second substrate region electrically isolated from each other;

a first MOS field effect transistor of a first conduction type and a first capacitor which are formed in said first substrate region; and

a second MOS field effect transistor of a second conduction type and a second capacitor which are formed in said second substrate region;

wherein a single unit semiconductor device is formed by at least said first and second MOS field effect transistors and said first and second capacitors; and

a circuit configuration is formed by a semiconductor device group including at least said single unit semiconductor device, said first capacitor including one electrode connected to a gate electrode of said first MOS field effect transistor; and

another electrode connected to a source of said first MOS field effect transistor via a first resistor and a device substrate of said first MOS field effect transistor; and

said second capacitor including one electrode connected to a gate electrode of said second MOS field effect transistor; and

another electrode connected to a source of said first MOS field effect transistor via a second resistor and a device substrate of said first MOS field effect transistor.

14. A semiconductor integrated circuit as claimed in claim 10,

wherein said semiconductor device is isolated from the supporting substrate of the semiconductor integrated circuit by an insulator, and is isolated from another semiconductor device by an insulator.

41. A semiconductor integrated circuit as claimed in any one of claims 9 to 16,

wherein two pairs of semiconductor integrated circuits form a single unit memory.

46. A semiconductor integrated circuit as claimed in any one of claims 9, 10, 13, and 14,

wherein said resistor is formed by a resistive functional device having linear or nonlinear properties, and a resistance value of said resistor is set higher than on resistances of the first transistor and the third transistor.

47. A semiconductor integrated circuit as claimed in any one of claims 2, 6, 10, 14, 18, and 22,

wherein a relation between source-drain current (IDS) of a transistor, a resistance value (RS) of a resistor, a capacitance value (CG) of a capacitor, and driven load capacitance (CL) is set such that a product of CG, RS, and ISD is equal to or greater than CL.

11. A semiconductor integrated circuit comprising:

a supporting substrate having at least a first substrate region and a second substrate region electrically isolated from each other;

a first MOS field effect transistor of a first conduction type, a second MOS field effect transistor of the first conduction type, and a third MOS field effect transistor of a second conduction type which are formed in said first substrate region; and

a fourth MOS field effect transistor of the second conduction type, a fifth MOS field effect transistor of the second conduction type, and a sixth MOS field effect transistor of the first conduction type which are formed in said second substrate region;

wherein a single unit semiconductor device is formed by at least said first to sixth MOS field effect transistors; and

a circuit configuration is formed by a semiconductor device group including at least said single unit semiconductor device, said second MOS field effect transistor including a gate electrode connected to a gate electrode of said first MOS field effect transistor;

a drain connected to a drain of said first MOS field effect transistor; and

a source connected to a device substrate of said first MOS field effect transistor, said second MOS field effect transistor sharing a device substrate with said first MOS field effect transistor;

said fourth MOS field effect transistor including a gate electrode connected to a gate electrode of said first MOS field effect transistor; and

a drain connected to a drain of said first MOS field effect transistor; and

said fifth MOS field effect transistor including a gate electrode connected to a gate electrode of said first MOS field effect transistor;

a drain connected to a device substrate of said fourth MOS field effect transistor; and

a source connected to a source of said fourth MOS field effect transistor.

12. A semiconductor integrated circuit as claimed in claim 11,

wherein said third MOS field effect transistor is of the first conduction type and has a gate electrode connected to the drain of said first transistor;

and

said sixth MOS field effect transistor is of the second conduction type and has a gate electrode connected to the drain of said first transistor.

15. A semiconductor integrated circuit as claimed in claim 11,

wherein said semiconductor device is isolated from the supporting substrate of the semiconductor integrated circuit by an insulator, and is isolated from another semiconductor device by an insulator.

16. A semiconductor integrated circuit as claimed in claim 12,

wherein said semiconductor device is isolated from the supporting substrate of the semiconductor integrated circuit by an insulator, and is isolated from another semiconductor device by an insulator.

19. A semiconductor integrated circuit as claimed in claim 17,

wherein said resistor is replaced with a third MOS field effect transistor of a second conduction type, and a gate electrode of said third transistor is connected to one input node.

20. A semiconductor integrated circuit as claimed in claim 19,

wherein said third transistor is replaced with a third MOS field effect transistor of a first conduction type, and a gate electrode of said third MOS field effect transistor is connected to an output node.

21. A semiconductor integrated circuit as claimed in claim 17,

wherein the resistor and a plurality of the groups of the transistors sharing device substrate nodes to form series connections are isolated from a supporting substrate of the semiconductor integrated circuit by an insulator, and are isolated by an insulator from another semiconductor device that does not share the device substrate nodes.

22. A semiconductor integrated circuit as claimed in claim 18,

wherein said semiconductor devices are isolated from a supporting substrate of the semiconductor integrated circuit by an insulator, and are isolated from each other by an insulator.

23. A semiconductor integrated circuit as claimed in claim 19,

wherein said semiconductor devices are isolated from a supporting substrate of the semiconductor integrated circuit by an insulator, and are isolated from each other by an insulator.

24. A semiconductor integrated circuit as claimed in claim 20,

wherein said semiconductor devices are isolated from a supporting substrate of the semiconductor integrated circuit by an insulator, and are isolated from each other by an insulator.

27. A semiconductor integrated circuit as claimed in claim 26,

wherein a capacitor is added between a gate electrode and the body node of said first transistor.

32. A semiconductor integrated circuit as claimed in claims 3, 4, 7, 8, 19, 20, and 23 to 25,

wherein absolute values of threshold voltages of said second transistor and said third transistor are set lower than an absolute value of threshold voltage of said first transistor.

34. A semiconductor integrated circuit as claimed in claims 11, 12, 15, and 16,

wherein absolute values of threshold voltages of said second transistor, said third transistor, said fifth transistor, and said sixth transistor are set lower than absolute values of threshold voltages of said first transistor and said fourth transistor.

36. A semiconductor integrated circuit as claimed in claims 3, 4, 7, 8, 19, 20, and 23 to 25,

wherein channel widths of said second transistor and said third transistor are ⅕

or less of channel width of said first transistor.

38. A semiconductor integrated circuit as claimed in claims 11, 12, 15, and 16,

wherein channel widths of said second transistor, said third transistor, said fifth transistor, and said sixth transistor are ⅕

or less of channel widths of said first transistor and said fourth transistor.

39. A semiconductor integrated circuit as claimed in claim 29,

wherein said resistor is formed in a single crystalline semiconductor layer between source and drain junctions of a MOS field effect transistor and a buried insulator.

17. A semiconductor integrated circuit comprising:

a plurality of sets of first MOS field effect transistors of a first conduction type and second MOS field effect transistors of the first conduction type which correspond to a plurality of input nodes, one of the first MOS field effect transistors and one of the second MOS field effect transistors together forming one set and having gate electrodes connected to one input node;

wherein a group of the first transistors in the sets of said transistors share a body node to form a first series connection; and

a group of the second transistors in the sets of said transistors share a body node to form a second series connection, one end of each of said first and second series connections being connected to an output node;

another end of said first series connection being connected to a power supply node; and

another end of said second series connection being connected to said body node and said power supply node via a resistor, whereby a portion of a NAND type gate circuit or a NOR type gate circuit is formed.

25. A semiconductor integrated circuit comprising:

a first MOS field effect transistor; and

a second MOS field effect transistor and a third MOS field effect transistor each having a gate electrode connected to a gate electrode of the first MOS field effect transistor, said second transistor including a source and a drain connected to a source and a body node of said first transistor, respectively, and said third transistor including a source and a drain connected to the body node and a drain of said first transistor, respectively.

42. A semiconductor integrated circuit as claimed in any one of claims 25 to 27,

wherein one node of a MOS field effect transistor is connected with a capacitor, whereby a single unit memory is formed.

26. A semiconductor integrated circuit comprising:

a first MOS field effect transistor of a first conduction type; and

a second transistor and a third transistor each of a second conduction type and respectively controlled by a source and a drain of the first MOS field effect transistor, said second transistor including a source connected to the source of said first transistor via a first resistor; and

a drain connected to a body node of said first transistor; and

said third transistor including a source connected to the body node of said first transistor; and

a drain connected to the drain of said first transistor via a second resistor.

40. A method of fabrication of a semiconductor integrated circuit, comprising the steps of:

forming a gate electrode on a principal surface of a single crystalline semiconductor layer of a first conduction type isolated from a supporting substrate by a thick insulator with a thin insulator intermediate between the gate electrode and the principal surface of the single crystalline semiconductor layer;

forming a shallow diffusion layer of a second conduction type with said gate electrode serving as a mask position;

forming a deep source or drain diffusion layer of the second conduction type in a section of a region where said shallow diffusion layer is formed so as not to allow a bottom of a source or drain junction to reach said thick insulator;

creating holes whose bottoms reach said thick insulator in a section of the single crystalline semiconductor layer where only said shallow diffusion layer is formed and in a section of the single crystalline semiconductor layer where the deep diffusion layer is formed; and

forming conductive layers in said holes and thereby short-circuiting a region of the first conduction type and a region of the second conduction type.