Double LDD devices for improved DRAM refresh

• US 20020195626A1
• Filed: 08/01/2002
• Published: 12/26/2002
• Est. Priority Date: 08/22/2000
• Status: Active Grant

• Current Assignee: Round Rock Research LLC
• Original Assignee: Luan C. Tran, Mark Mcqueen, Robert Kerr
• Inventors: Tran, Luan C., Kerr, Robert, McQueen, Mark
• Granted Patent: US 6,759,288 B2
• Time in Patent Office: Days
• US Class Current: 257/285
• CPC Class Codes: H01L 29/6653 using the removal of at least part of spacer, e.g. disposable spacer
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H10B 12/09 with simultaneous manufacture of the peripheral circuit region and memory cells
• CPC Class Codes: H10B 12/50 Peripheral circuit region structures

Abstract

An integrated circuit device with improved DRAM refresh characteristics, and a novel method of making the device, is provided. A semiconductor substrate is provided with gate structures formed on its surface in each of an array portion and a peripheral portion. Single lightly doped regions are formed adjacent to the channel regions by ion implantation in the substrate. Dielectric spacers having a first width are formed on the substrate surface adjacent to the gate structures covering at least a portion of the single lightly doped regions. Heavily-doped regions are ion-implanted on opposite sides of the gate structure in the peripheral portion. The dielectric spacers are etched back to a second width smaller than the first width. Double lightly doped regions are formed by ion implantation in the substrate in an area of the substrate left exposed by the spacer etch back. Triple lightly doped regions may be also be formed by a first implant at the gate edge, a second implant through an intermediate spacer, and a third implant after the spacer etch back.

Claims

1. A method of forming an access transistor of a memory cell, said method comprising:

forming a gate structure on a substrate, said gate structure defining a channel region of said access transistor;

forming double lightly doped regions on opposite sides of said gate structure; and

forming single lightly doped regions between each of said double lightly doped regions and said channel region.

2. The method of claim 1 wherein said channel region is doped with a doping concentration up to about 30% less than a doping concentration of a channel region of an access transistor not having said single and double lightly doped regions.

3. The method of claim 1, further comprising forming a dielectric layer on said gate structure and said substrate before forming said single lightly doped region.

4. The method of claim 1 further comprising forming a dielectric layer on said gate structure and said substrate after forming said single lightly doped region.

5. The method of claim 4 further comprising forming a triple lightly doped region in said substrate adjacent said double lightly doped region, wherein said double lightly doped region lies between said single lightly doped region and said triple lightly doped region.

6. The method of claim 3 wherein said forming of said dielectric layer includes depositing oxide to a thickness of between about 30 and about 200 angstroms.

7. The method of claim 3 wherein said forming of said dielectric layer includes depositing nitride to a thickness of between about 30 and about 200 angstroms.

8. The method of claim 3 wherein said forming of said dielectric layer includes depositing oxynitride to a thickness of between about 30 and about 200 angstroms.

9. The method of claim 3 wherein said forming of said dielectric layer includes depositing tetraethylorthosilicate (TEOS) to a thickness of between about 30 and about 200 angstroms.

10. The method of claim 5 wherein said forming of said dielectric layer includes depositing oxide to a thickness of between about 30 and about 200 angstroms.

11. The method of claim 5 wherein said forming of said dielectric layer includes depositing nitride to a thickness of between about 30 and about 200 angstroms.

12. The method of claim 5 wherein said forming of said dielectric layer includes depositing oxynitride to a thickness of between about 30 and about 200 angstroms.

13. The method of claim 5 wherein said forming of said dielectric layer includes depositing tetraethylorthosilicate (TEOS) to a thickness of between about 30 and about 200 angstroms.

14. The method of claim 1 further comprising forming a conductive plug overlying at least said double lightly doped region.

15. The method of claim 3 further comprising forming a conductive plug overlying at least said double lightly doped region.

16. The method of claim 5 further comprising forming a conductive plug overlying at least said triple lightly doped region.

18. The method of claim 17 wherein said semiconductor device is a peripheral device.

19. The method of claim 17 wherein said forming of said dielectric spacer includes forming on one side of said gate structure and said narrowing includes narrowing said dielectric spacer on one side of said gate structure.

20. The method of claim 17 wherein said forming of said dielectric spacer includes forming on both sides of said gate structure and said narrowing includes narrowing said dielectric spacer on both sides of said gate structure.

21. The method of claim 17 wherein said act of forming said double lightly doped region is performed subsequent to said acts of forming said heavily doped region and narrowing said dielectric spacer.

22. The method of claim 17, further comprising forming a dielectric layer on said gate structure and said substrate before forming said single lightly doped region through said dielectric layer, wherein a portion of said dielectric layer is subsequently removed to form said spacer.

23. The method of claim 17 further comprising forming a dielectric layer on said gate structure and said substrate after forming said single lightly doped region, wherein a portion of said dielectric layer is removed to form said spacer.

24. The method of claim 23 further comprising forming a triple lightly doped region in said substrate adjacent said double lightly doped region, wherein said double lightly doped region lies between said single lightly doped region and said triple lightly doped region.

25. The method of claim 22 wherein said forming of said dielectric layer includes depositing tetraethylorthosilicate (TEOS) or other dielectrics to a thickness of between about 30 and about 200 angstroms.

26. The method of claim 23 wherein said forming of said dielectric layer includes depositing tetraethylorthosilicate (TEOS) or other dielectrics to a thickness of between about 30 and about 200 angstroms.

27. The method of claim 17 further comprising forming a halo implant region between said single lightly doped region and said channel region.

28. The method of claim 24 further comprising forming a halo implant region between said single lightly doped region and said channel region.

29. The method of claim 28 wherein said act of forming said single lightly doped region is performed subsequent to formation of said gate structure, said act of forming said double lightly doped region is performed through said dielectric layer, and said act of forming said triple lightly doped region is performed subsequent to said act of narrowing said dielectric spacer.

30. The method of claim 27 wherein said act of forming said halo implant region is performed subsequent to said act of forming said single lightly doped region and prior to said act of forming said double lightly doped region.

31. The method of claim 27 wherein said act of forming said halo implant region is performed prior to said act of forming said single lightly doped region and prior to said act of forming said double lightly doped region.

32. The method of claim 27 wherein said act of forming said halo implant region is performed subsequent to said act of forming said single lightly doped region and subsequent to said act of forming said double lightly doped region.

17. A method of forming a semiconductor device, comprising:

forming a single lightly doped region in a substrate adjacent a channel region, said channel region residing below a gate structure formed on said substrate;

forming a dielectric spacer on at least one side of said gate structure;

forming a heavily doped region in a portion of said substrate not covered by said dielectric spacer and adjacent said single lightly doped region;

narrowing said dielectric spacer on said at least one side of said gate structure; and

forming a double lightly doped region in said substrate between said heavily doped region and said single lightly doped region.

33. A method of forming an access transistor of a memory cell, said method comprising:

forming a gate structure of said access transistor on a substrate, said gate structure defining a channel region of said access transistor;

performing a first lightly doped implant on each side of said gate structure;

forming side spacers on the sides of said gate structure;

performing a second lightly doped implant on each side of said gate structure and associated spacers to produce double lightly doped source and drain regions of said access transistor, each of which has a single lightly doped region between it and said channel region.

35. The method of claim 34 wherein said first and second gate structures are formed at a same time.

36. The method of claim 34 further comprising performing a halo implant on each side of said second gate structure through a sidewall spacer after said memory array portion is masked and before performing said heavily doped implant.

38. The method of claim 37 wherein said removing of said portion of said spacer causes said second spacer width to be about 25 to about 75 percent of said first spacer width.

39. The method of claim 37 further comprising forming at least one halo implant region in said periphery portion between said single lightly doped region and said channel region.

40. The method of claim 39 wherein said forming of said halo implant region includes tilt-angle doping of said periphery portion of said substrate with p-type dopant ions at an angle between about 0 and about 45 degrees.

41. The method of claim 40 wherein said p-type dopant is boron or indium.

42. The method of claim 39 wherein said forming of said halo implant region includes tilt-angle doping of said periphery portion of said substrate with n-type dopant ions at an angle between about 0 and about 45 degrees.

43. The method of claim 42 wherein said n-type dopant is phosphorus, arsenic or antimony.

44. The method of claim 37 further comprising forming a dielectric layer on said gate structure and said substrate before forming said single lightly doped region, wherein a portion of said dielectric layer is removed to form said spacer.

45. The method of claim 44 wherein said dielectric layer is formed from a material different from a material of said dielectric spacer.

46. The method of claim 37 further comprising forming a dielectric layer on said gate structure and said substrate after forming said single lightly doped region, wherein a portion of said dielectric layer is removed to form said spacer.

47. The method of claim 46 wherein said dielectric layer is formed from a material different from a material of said dielectric spacer.

48. The method of claim 46 further comprising forming at least one triple lightly doped region in said substrate adjacent said double tightly doped region in said array portion, wherein said double lightly doped region of said array portion lies between said single lightly doped region and said triple lightly doped region in said array portion.

49. The method of claim 44 wherein said forming of said dielectric layer includes depositing tetraethylorthosilicate (TEOS) or other dielectrics to a thickness of between about 30 and about 200 angstroms.

50. The method of claim 48 wherein said forming of said dielectric layer includes depositing tetraethylorthosilicate (TEOS) or other dielectrics to a thickness of between about 30 and about 200 angstroms.

51. The method of claim 44 wherein said forming of said dielectric layer includes depositing a dielectric material to a thickness of between about 25 to about 50 percent of said first spacer width.

52. The method of claim 46 wherein said forming of said dielectric layer includes depositing a dielectric material to a thickness of between about 25 to about 50 percent of said first spacer width.

53. The method of claim 37 further comprising forming at least one conductive plug in said array portion adjacent said spacer overlying at least said double lightly doped region.

54. The method of claim 44 further comprising forming at least one conductive plug in said array portion adjacent said spacer overlying at least said double lightly doped region.

55. The method of claim 48 further comprising forming at least one conductive plug in said array portion adjacent said spacer overlying at least said triple is lightly doped region.

57. The integrated circuit device of claim 56, further comprising a triple lightly doped region formed in said substrate adjacent said double lightly doped region, wherein said double lightly doped region lies between said single lightly doped region and said triple lightly doped region.

58. The integrated circuit device of claim 56, further comprising a conductive plug overlying at least said double lightly doped region.

59. The integrated circuit device of claim 57, further comprising a conductive plug overlying at least said triple lightly doped region.

34. A method of forming at least one access transistor of a memory cell in an array portion of a memory device and another transistor of a peripheral circuit portion of said memory device, said method comprising:

forming a first gate structure of said access transistor in said memory array portion and a second gate structure of said another transistor in said peripheral circuit portion on a substrate, said first and second gate structures defining respective channel regions of said access transistor and said another transistor;

performing a first lightly doped implant on each side of said first and second gate structures;

forming spacers on the sides of said first and second gate structures;

masking said memory array portion;

performing a heavily doped implant on each side of said second gate structure;

removing the masking of said memory array portion;

reducing the width of said spacers on the sides of said first and second gate structures; and

performing a second lightly doped implant on each side of said first and second gate structures.

37. A method of forming a memory device including a memory array portion and a peripheral logic portion, comprising:

forming at least one gate structure in an array portion of the device and at least one gate structure in a periphery portion of the device, whereby each said gate structure controls charge carriers in a respective channel region of said substrate;

forming a single lightly doped region in said substrate on opposite sides of each said respective channel region;

forming a dielectric spacer having a first width adjacent opposite sides of each of said gate structures, wherein a portion of said single lightly doped region underlies said spacer;

forming a heavily-doped region in said substrate on opposite sides of said gate structure in said periphery portion;

removing a portion of said spacer from the sides of said gate structure such that said spacer has a second width smaller than said first width; and

forming a double lightly doped region in said substrate adjacent said single lightly doped region, wherein said double lightly doped region underlies a former position of said removed portion of said spacer.

56. An integrated circuit device in a memory array, comprising:

a gate structure formed on and supported by a memory array portion of a substrate;

a channel region formed in said substrate in said array portion;

a single lightly doped region formed in said substrate in said array portion adjacent said channel region; and

a double lightly doped region formed in said substrate in said array portion adjacent said single lightly doped region, wherein said single lightly doped region lies between said double lightly doped region and said channel region.

60. A memory device, comprising:

a substrate including an array portion and a periphery portion;

at least two gate structures formed on and supported by said substrate, wherein at least one gate structure is formed in each of said array portion and said periphery portion;

dielectric spacers formed on opposite sides of said gate structures;

at least two channel regions formed in said substrate below said gate structures, wherein each said gate structure controls charge carriers in a respective channel region;

single lightly doped regions formed in said substrate on opposite sides of each said respective channel region;

double lightly doped regions formed in said substrate adjacent each of said single lightly doped regions, wherein one of said single lightly doped regions lies between one of said double lightly doped regions and said respective channel region;

heavily-doped regions formed in said substrate in said periphery portion, wherein one of said single lightly doped regions and one of said double lightly doped regions lie between each of said heavily-doped regions and said respective channel region.

61. The memory device of claim 60, further comprising triple lightly doped regions formed in said substrate adjacent said double lightly doped regions, wherein one of said double lightly doped regions lies between one of said single lightly doped regions and one of said triple lightly doped regions.

62. The memory device of claim 60, further comprising halo implant regions formed in said substrate in said periphery portion, wherein one of said halo implant regions lies between one of said single lightly doped regions and said respective channel region.

63. The memory device of claim 60, further comprising at least one conductive plug formed in said array portion adjacent at least one of said spacers, wherein said conductive plug overlies one of said double lightly doped regions.

64. The memory device of claim 61, further comprising at least one conductive plug formed in said array portion adjacent at least one of said spacers, wherein said conductive plug overlies one of said triple lightly doped regions.

65. A processor-based system, comprising:

a processor;

an integrated memory circuit connected to said processor, said memory circuit comprising;

a gate structure formed on and supported by a memory array portion of a substrate;

a channel region formed in said substrate in said array portion;

a single lightly doped region formed in said substrate in said array portion adjacent said channel region; and

a double lightly doped region formed in said substrate in said array portion adjacent said single lightly doped region, wherein said single lightly doped region lies between said double lightly doped region and said channel region.

66. The processor-based system of claim 65, further comprising a triple lightly doped region formed in said substrate adjacent said double lightly doped region, wherein said double lightly doped region lies between said single lightly doped region and said triple lightly doped region.

67. The processor-based system of claim 65, further comprising a conductive plug overlying at least said double lightly doped region.

68. The processor-based system of claim 66, further comprising a conductive plug overlying at least said triple lightly doped region.

69. A processor-based system, comprising:

a processor;

an integrated memory circuit connected to said processor, said memory circuit comprising;

a substrate including an array portion and a periphery portion;

at least two gate structures formed on and supported by said substrate, wherein at least one gate structure is formed in each of said array portion and said periphery portion;

dielectric spacers formed on and supported by said substrate on opposite sides of said gate structures;

at least two channel regions formed in said substrate, wherein each said gate structure controls charge carriers in a respective channel region;

single lightly doped regions formed in said substrate on opposite sides of each said respective channel region;

double lightly doped regions formed in said substrate adjacent each of said single lightly doped regions, wherein one of said single lightly doped regions lies between one said double lightly doped regions and said respective channel region;

heavily-doped regions formed in said substrate in said periphery portion, wherein one of said single lightly doped regions and one of said double lightly doped regions lie between each of said heavily-doped regions and said respective channel region.

70. An embedded-memory processor-based system, comprising:

a processor;

a memory circuit formed on a same integrated circuit as said processor, said memory circuit comprising;

a gate structure formed on and supported by a memory array portion of a substrate;

a channel region formed in said substrate in said array portion;

a single lightly doped region formed in said substrate in said array portion adjacent said channel region; and

a double lightly doped region formed in said substrate in said array portion adjacent said single lightly doped region, wherein said single lightly doped region lies between said double lightly doped region and said channel region.

71. The embedded-memory processor-based system of claim 70, further comprising a triple lightly doped region formed in said substrate adjacent said double lightly doped region, wherein said double lightly doped region lies between said single lightly doped region and said triple lightly doped region.

72. The embedded-memory processor-based system of claim 70, further comprising a conductive plug overlying at least said double lightly doped region.

73. The embedded-memory processor-based system of claim 71, further comprising a conductive plug overlying at least said triple lightly doped region.

74. An embedded-memory processor-based system, comprising:

a processor;

a memory circuit formed on a same integrated circuit as said processor, said memory circuit comprising;

a substrate including an array portion and a periphery portion;

at least two gate structures formed on and supported by said substrate, wherein at least one gate structure is formed in each of said array portion and said periphery portion;

dielectric spacers formed on and supported by said substrate on opposite sides of said gate structures;

at least two channel regions formed in said substrate, wherein each said gate structure controls charge carriers in a respective channel region;

single lightly doped regions formed in said substrate on opposite sides of each said respective channel region;

double lightly doped regions formed in said substrate adjacent each of said single lightly doped regions, wherein one of said single lightly doped regions lies between one said double lightly doped regions and said respective channel region;

heavily-doped regions formed in said substrate in said periphery portion, wherein one of said single lightly doped regions and one of said double lightly doped regions lie between each of said heavily-doped regions and said respective channel region.