Organic polarizable gate transistor apparatus and method

• US 20020195644A1
• Filed: 06/08/2001
• Published: 12/26/2002
• Est. Priority Date: 06/08/2001
• Status: Active Grant

• Current Assignee: Alcatel-Lucent USA, Inc. (Nokia Corporation)
• Original Assignee: Ananth Dodabalapur, Howard E. Katz, Rahul Sarpeshkar
• Inventors: Katz, Howard E., Sarpeshkar, Rahul, Dodabalapur, Ananth
• Granted Patent: US 6,870,180 B2
• Time in Patent Office: Days
• US Class Current: 257/314
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: G11C 13/0014 comprising cells based on organic memory material
• CPC Class Codes: G11C 13/0016 comprising polymers
• CPC Class Codes: H01L 21/28167 on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
• CPC Class Codes: H01L 29/51 Insulating materials associated therewith for MIS structures on thin film semiconductor H01L29/4908
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/792 with charge trapping gate insulator, e.g. MNOS-memory transistors
• CPC Class Codes: H10K 10/466 Lateral bottom-gate IGFETs comprising only a single gate
• CPC Class Codes: H10K 10/471 the gate dielectric comprising only organic materials
• CPC Class Codes: H10K 10/472 the gate dielectric comprising only inorganic materials
• CPC Class Codes: H10K 85/621 Aromatic anhydride or imide compounds, e.g. perylene tetra-carboxylic dianhydride or perylene tetracarboxylic di-imide
• CPC Class Codes: H10K 85/655 comprising only sulfur as heteroatom

Abstract

An apparatus having a circuit coupled to the gate contact of a field effect transistor wherein the transistor'"'"'s gate includes a dielectric layer of which at least a portion is an organic dielectric. The circuit is configured to produce one or more storage voltage pulses that cause charge to be stored in the gate. The field effect transistor has a semiconductor layer with a conductive path whose conductivity changes for a given V_g in response to storing the charge. The circuit may produce one or more dissipation voltage pulses having a voltage of opposite sign to the one or more storage pulses, that cause dissipation of charge stored in the gate. Further disclosed are a memory and a method of electronically storing and reading information, both utilizing the organic-based polarizable gate transistor apparatus.

Claims

1. An apparatus, comprising:

a field effect transistor having a gate, the gate including a dielectric layer, wherein at least a portion of the dielectric layer is an organic dielectric, and a gate contact; and

a circuit having an output coupled to the gate contact, the circuit is configured to produce one or more storage voltage pulses that cause charge to be stored in the gate.

2. The apparatus of claim 1 wherein the charge is stored in at least a portion of the dielectric layer.

3. The apparatus of claim 1, wherein the FET further comprises a source and a drain, and the conductivity of a conductive path between the source and the drain for a given gate voltage is changed in response to storing a charge.

4. The apparatus of claim 1, wherein the dielectric layer includes a charge storage layer.

5. The apparatus of claim 4, wherein the charge storage layer is selected from the group consisting of cyclic olefin copolymer, glass resin, poly (4 methylstyrene), TiO₂-siloxane composites, zinc octaethylporphyrin films, anthracene-methacrylate copolymers, poly(methylmethacrylate), poly-tetrafluoroethylene, copolymers of substituted styrenes, and composites of polymers with particles or pores that retain static charges.

6. The apparatus of claim 1, wherein the dielectric layer includes a semiconductor interface layer.

7. The apparatus of claim 6, wherein the semiconductor interface layer is selected from the group consisting of glass resin, self assembled monolayer and polymer.

8. The apparatus of claim 1, wherein at least a portion of the dielectric layer is hydrophobic.

9. The apparatus of claim 1, further comprising:

a memory cell, the transistor being an information storage device of the cell.

10. The apparatus of claim 1, wherein the field effect transistor further comprises a channel, the channel including an organic semiconductor.

11. The apparatus of claim 1, wherein the FET further comprises an organic semiconductor layer.

12. The apparatus of claim 11, wherein the organic semiconductor is selected from the group consisting of phenylene-thiophene oligomers, NTCDI compounds, thiophene-thiazole oligomers, and benzodithiophene-based compounds.

13. The apparatus of claim 11, wherein the organic semiconductor is selected from the group consisting of phenylene oligomers and co-oligomers and copolymers of thiophene and fluorene.

14. The apparatus of claim 1, wherein the circuit is configured to produce one or more dissipation voltage pulses that cause dissipation of charge stored in the gate dielectric, the one or more dissipation pulses having a voltage of opposite sign to the one or more storage pulses.

15. The apparatus of claim 14, wherein the one or more storage and the one or more dissipation voltage pulses correspond to voltages whose magnitudes are at least three times as large as a voltage that causes a channel in the field effect transistor to conduct.

16. The apparatus of claim 1, wherein the circuit is configured to produce one or more types of energy that cause dissipation of charge stored in the gate dielectric.

17. The apparatus of claim 16 wherein the energy is in a form selected from the group consisting of heat and light.

18. The apparatus of claim 1, wherein the field effect transistor further comprises a channel and the circuit is configured to produce a voltage pulse that changes the conductivity of the channel by at least a factor of ten.

19. The apparatus of claim 1, wherein the organic gate dielectric has a thickness and the circuit is configured to produce a voltage pulse, and wherein the ratio of the voltage to the thickness is in the range of about 10V/1 μ

to about 200V/1 μ

.

20. The apparatus of claim 1 wherein the circuit is selected from the group consisting of CMOS compatible floating gate elements, analog memory elements, capacitor-based circuits, adaptive circuits, learning networks and pixel.

21. The apparatus of claim 1 wherein the gate comprises a source, drain and an auxiliary electrode, and wherein the circuit output is coupled to the auxiliary electrode.

22. The apparatus of claim 1 wherein charge is implanted in the dielectric layer by microcontact printing.

24. The method of claim 23, wherein the transistor is an information storage device of a memory cell, and the method further comprises:

storing information in the transistor.

25. The method of claim 23, utilizing a field effect transistor comprising an organic semiconductor.

26. The method of claim 23, further comprising:

erasing at least some stored information by dissipating at least some charge stored in the gate dielectric.

27. The method of claim 26, wherein the stored charge is dissipated by the circuit providing one or more dissipation voltage pulses, the one or more dissipation pulses having a voltage of opposite sign to the one or more storage pulses.

28. The method of claim 26, wherein the stored charge is dissipated by the circuit providing one or more types of energy.

29. The method of claim 28 wherein the energy is in a form selected from the group consisting of heat and light.

23. A method of electronically storing and reading information utilizing:

a field effect transistor having a gate, the gate including a dielectric layer, wherein at least a portion of the dielectric layer is an organic dielectric, and a gate contact; and

a circuit having an output coupled to the gate contact;

the steps of the method comprising;

storing charge in the gate by the circuit supplying one or more storage voltage pulses to the gate.

30. A memory, comprising:

a plurality of memory cells;

wherein at least one memory cell comprises;

a field effect transistor having a gate, the gate including a dielectric layer, wherein at least a portion of the dielectric layer is an organic dielectric, and a gate contact; and

a circuit having an output coupled to at least two of the gate contacts, the circuit configured to produce one or more storage voltage pulses that cause charge storage in the gate dielectric.

31. The memory of claim 30, wherein the field effect transistor has a channel, the channel including an organic semiconductor.

32. The memory of claim 30, wherein the circuit is configured to produce one or more dissipation voltage pulses that cause dissipation of charge stored in the gate dielectric, the one or more dissipation pulses having a voltage of opposite sign to the one or more storage voltage pulses.