Symmetric trench MOSFET device and method of making same

• US 20020195655A1
• Filed: 06/14/2001
• Published: 12/26/2002
• Est. Priority Date: 06/14/2001
• Status: Active Grant

• Current Assignee: General Semiconductor, Inc. (Vishay Intertechnology Incorporated)
• Original Assignee: General Semiconductor, Inc. (Vishay Intertechnology Incorporated)
• Inventors: Hshieh, Fwu-Iuan, Blanchard, Richard A., So, Koon Chong
• Granted Patent: US 6,777,745 B2
• Time in Patent Office: Days
• US Class Current: 257/330
• CPC Class Codes: H01L 21/823487 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823431
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/51 Insulating materials associated therewith for MIS structures on thin film semiconductor H01L29/4908
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence

Abstract

A trench MOSFET transistor device and method of making the same are provided. The trench MOSFET transistor device comprises: (a) a drain region of first conductivity type; (b) a body region of a second conductivity type provided over the drain region, such that the drain region and the body region form a first junction; (c) a source region of the first conductivity type provided over the body region, such that the source region and the body region form a second junction; (d) source metal disposed on an upper surface of the source region; (e) a trench extending through the source region, through the body region and into the drain region; and (f) a gate region comprising (i) an insulating layer, which lines at least a portion of the trench and (ii) a conductive region, which is disposed within the trench adjacent the insulating layer. The body region in this device is separated from the source metal. Moreover, the doping profile within the body region and within at least a portion of the source and drain regions, when taken along a line normal to upper and lower surfaces of the device, is such that the doping profile on one side of a centerplane of the body region is symmetric with the doping profile on an opposite side of the centerplane.

Claims

1. A trench MOSFET transistor device comprising:

a drain region of a first conductivity type;

a body region of a second conductivity type provided over said drain region, said drain region and said body region forming a first junction;

a source region of said first conductivity type provided over said body region, said source region and said body region forming a second junction;

source metal disposed on an upper surface of said source region;

a trench extending through said source region, through said body region and into said drain region; and

a gate region comprising an insulating layer lining at least a portion of said trench and a conductive region within said trench adjacent said insulating layer,

wherein (a) said body region is separated from said source metal, and (b) a doping profile along a line normal to upper and lower surfaces of said device is such that, within said body region and within at least a portion of said source and drain regions, the doping profile on one side of a centerplane of the body region is symmetric with the doping profile on an opposite side of the centerplane.

2. The trench MOSFET transistor device of claim 1, wherein said body region is separated from said source metal by said source region.

3. The trench MOSFET transistor device of claim 1, further comprising gate metal adjacent said conductive region.

4. The trench MOSFET transistor device of claim 1, wherein the body region further comprises a material that provides generation-recombination centers.

5. The trench MOSFET transistor device of claim 4, wherein said material is selected from gold and platinum.

6. The trench MOSFET transistor device of claim 1, wherein said source, drain and body regions are doped silicon regions.

7. The trench MOSFET transistor device of claim 6, wherein said conductive region is doped polycrystalline silicon.

8. The trench MOSFET transistor device of claim 6, wherein said insulating layer is a silicon dioxide layer.

9. The trench MOSFET transistor device of claim 6, wherein said insulating layer is a silicon oxynitride layer.

10. The trench MOSFET transistor device of claim 1, wherein a fixed charge is provided within said insulating layer.

11. The trench MOSFET transistor device of claim 1, wherein said source and drain regions have peak net doping concentrations that are greater than a peak net doping concentration of said body region.

12. The trench MOSFET transistor device of claim 1, wherein said first conductivity type is N-type conductivity and said second conductivity type is P-type conductivity.

13. The trench MOSFET transistor device of claim 1, wherein said source and drain regions comprise the same dopant material.

15. The trench MOSFET transistor device of claim 14, wherein said doping material comprises arsenic.

16. The trench MOSFET transistor device of claim 14, wherein said doping material comprises phosphorous.

18. The method of claim 17, wherein said drain region, said body region and said source region are provided by a method comprising:

providing a substrate of first conductivity type;

depositing an epitaxial layer upon said substrate; and

performing a source dopant ion implantation step and a body dopant ion implantation step such that the peak of the body dopant after implantation is one-half of the distance from the peak of the source dopant to the peak of the drain dopant.

19. The method of claim 17, wherein said drain region, said body region and said source region are provided by a method comprising:

providing a substrate of N-type conductivity;

implanting a first dose of P-type body dopant into said substrate;

depositing an N-type epitaxial layer over the implanted substrate;

implanting a second dose of P-type body dopant into said epitaxial layer; and

implanting an N-type source dopant into said epitaxial layer.

20. The method of claim 17, wherein said first conductivity type is N-type conductivity, wherein said second conductivity type is P-type conductivity, and wherein said drain region, said body region and said source region are provided by a method comprising:

providing a substrate of N-type conductivity;

depositing an epitaxial layer over said substrate;

implanting boron into said epitaxial layer;

growing an oxide layer on a surface of said epitaxial layer; and

implanting an N-type source dopant into said epitaxial layer.

21. The method of claim 17, wherein said drain region, said body region and said source region are formed by a method comprising:

providing a substrate of first conductivity type;

depositing an epitaxial layer of second conductivity type over said substrate; and

implanting source dopant of first conductivity type into said epitaxial layer.

22. The method of claim 17, wherein said body region and said source region are formed prior to trench formation.

23. The method of claim 17, wherein said body region is formed before trench formation and said source region is formed after trench formation.

24. The method of claim 17,

wherein said drain, body and source regions are silicon regions,

wherein said insulating layer is a silicon dioxide layer,

wherein said conductive region is a doped polycrystalline silicon region,

wherein said first conductivity type is N-type conductivity,

wherein said second conductivity type is P-type conductivity,

wherein said source and drain regions comprise the same doping material, and

wherein said source and drain regions have peak net doping concentrations that are greater than a peak net doping concentration of said body region.

14. A trench MOSFET transistor device comprising:

a silicon drain region of N-type conductivity;

a silicon body region of P-type conductivity provided over said drain region, said drain region and said body region forming a first junction;

a silicon source region of N-type conductivity provided over said body region, said source region and said body region forming a second junction;

source metal disposed on an upper surface of said source region;

a trench extending through said source region, through said body region and into said drain region; and

a gate region comprising a silicon dioxide layer lining at least a portion of said trench and a doped polycrystalline silicon region within said trench adjacent said silicon dioxide layer,

wherein (a) said body region is separated from said source metal by said source region, (b) said source and drain regions comprise the same doping material, (c) said source and drain regions have peak net doping concentrations that are greater than a peak net doping concentration of said body region, and (d) a doping profile along a line normal to upper and lower surfaces of said device is such that, within said body region and within at least a portion of said source and drain regions, the doping profile on one side of a centerplane of the body region is symmetric with the doping profile on an opposite side of said centerplane.

17. A method of forming a trench MOSFET transistor device comprising:

providing a drain region of first conductivity type;

providing a body region of a second conductivity type over said drain region, said drain region and said body region forming a first junction;

providing a source region of said first conductivity type over said body region, said source region and said body region forming a second junction;

forming a trench that extends through said source region, through said body region and into said drain region;

forming an insulating layer over at least a portion of said trench;

providing a conductive region within said trench adjacent said insulating layer; and

providing source metal on an upper surface of said source region,

said method being performed such that (a) said body region is separated from said source metal, and (b) a doping profile along a line normal to upper and lower surfaces of said device is established in which, within said body region and within at least a portion of said source and drain regions, the doping profile on one side of a centerplane of the body region is symmetric with the doping profile on an opposite side of the centerplane.