Electrostatic discharge protection device

• US 20020195664A1
• Filed: 08/27/2002
• Published: 12/26/2002
• Est. Priority Date: 08/25/2000
• Status: Abandoned Application

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Marr, Kenneth W.
• Application Number:
  US10/228,725
• Publication Number:
  US 20020195664A1
• Time in Patent Office: Days
• US Class Current: 257/355
• CPC Class Codes: H01L 27/0266 using field effect transistors as protective elements

Abstract

An electrostatic discharge (ESD) protection device is provided. The ESD protection device includes a substrate, a first and a second doped region formed in the substrate. The first and second doped regions are separated from each other by only the substrate region. The ESD protection device includes no gate above the first and second doped regions. Furthermore, the distance separating the first and second doped regions is defined by a length of a resist during a process of forming the ESD protection device.

Claims

1. A method of producing a semiconductor device, the method comprising:

masking a substrate with a resist, the substrate having no gate structure over the substrate; and

forming a first dope region and a second doped region in the substrate, wherein the first and second doped regions are separated by only the substrate, wherein a spacing between the first and second doped regions is defined by a length of the resist between the first and second doped regions, wherein the method includes forming no gate above the substrate.

2. The method of claim 1, wherein:

the first and second doped regions have a first conductivity type; and

the substrate has a second conductivity type different from the first conductivity type.

3. The method of claim 1 further comprising:

forming a third doped region within the first doped region; and

forming a fourth doped region within the second doped region.

4. The method of claim 3, wherein:

the first and second doped regions have a first conductivity type; and

the third and fourth doped regions have a second conductivity type different from the first conductivity type.

5. The method of claim 4, wherein first and second doped regions have a higher doping concentration than the third and fourth doped regions.

6. The method of claim 4 further comprising:

forming a fifth doped region within the third source/drain region; and

forming sixth doped region within the fourth doped region.

7. The method of claim 6, wherein:

the fifth and sixth doped regions have a first conductivity type; and

the first and second doped regions have a second conductivity type different from the first conductivity type.

8. A method of producing a semiconductor device, the method comprising:

providing a substrate having no gate structure over the substrate;

masking a substrate with a resist having openings for forming a first unmasked region and a second unmasked region of the substrate, wherein the unmasked regions are separated by a length of the resist between the unmasked regions;

implanting dopants into the first and second unmasked regions to form a first source/drain region and a second source/drain regions; and

removing the resist, wherein the method includes forming no gate above the substrate.

9. The method of claim 8, wherein:

the first and second source/drain regions have a first conductivity type; and

the substrate has a second conductivity type different from the first conductivity type.

10. The method of claim 8 further comprising:

forming a first halo region surrounding the first source/drain region; and

forming second halo region surrounding the second source/drain region.

11. The method of claim 10 further comprising:

forming a first lightly doped region within the first source/drain region; and

forming second lightly doped region within the second source/drain region.

12. The method of claim 11, wherein:

the first and second lightly doped regions and the first and second source/drain regions have a first conductivity type.

the substrate and the first and second halo regions have a second conductivity type different from the first conductivity type.

13. The method of claim 11, wherein first and second source/drain regions have a higher doping concentration than the lightly doped regions.

15. The method of claim 14, wherein:

the first and second source/drain regions have a first conductivity type; and

the substrate has a second conductivity type different from the first conductivity type.

16. The method of claim 14 further comprising:

forming a first halo region surrounding the first source/drain region; and

forming second halo region surrounding the second source/drain region.

17. The method of claim 16 further comprising:

forming a first lightly doped region within the first source/drain region; and

forming second lightly doped region within the second source/drain region.

18. The method of claim 17, wherein:

the first and second lightly doped regions and the first and second source/drain regions have a first conductivity type.

the substrate and the first and second halo regions have a second conductivity type different from the first conductivity type.

19. The method of claim 17, wherein first and second source/drain regions have a higher doping concentration than the lightly doped regions.

14. A method of producing a semiconductor device, the method comprising:

providing a substrate having no gate structure over the substrate;

masking the substrate with a resist to define a first unmasked region and second unmasked region, the first and second unmasked regions being separated by a distance equaled to a length of a the resist between the first and second unmasked regions;

implanting dopants into the first and second unmasked regions to form a first source/drain region; and

removing the resist, wherein the method includes forming no gate above the substrate.

20. A method of making a semiconductor, the method comprising:

providing a substrate having no gate structure formed above the substrate;

forming a first halo region and a second halo region in the substrate;

forming a first lightly doped region within the first halo region;

forming a second lightly doped region within the second halo region;

forming a first source/drain region within the first lightly doped region; and

forming a second source/drain region within the second lightly doped region without forming a gate over the substrate, wherein the method includes forming no gate above the substrate.

21. The method of claim 20, wherein:

the first and second source/drain regions have a first conductivity type; and

the substrate has a second conductivity type different from the first conductivity type.

22. The method of claim 21, wherein:

the first and second source/drain regions have an n-type material; and

the substrate has a p-type material.

23. The method of claim 20, wherein:

the first and second lightly doped regions and the first and second source/drain regions have a first conductivity type, and

the substrate and the first and second halo regions have a second conductivity type different from the first conductivity type.

24. The method of claim 20, wherein first and second source/drain regions have a higher doping concentration than the first and second lightly doped regions.

25. The method of claim 20, wherein first and second source/drain regions have a higher doping concentration than the substrate.

27. The method of claim 26, wherein first and second source/drain regions have a higher doping concentration than the first and second lightly doped regions.

28. The method of claim 26, wherein first and second source/drain regions have a higher doping concentration than the substrate.

29. The method of claim 26, wherein:

the substrate and the first and second halo regions have a first conductivity type; and

the first and second lightly doped regions and the first and second source/drain regions have a second conductivity type different from the first conductivity type.

30. The method of claim 29, wherein:

the substrate and the first and second halo regions have a p-type material; and

the first and second lightly doped regions and the first and second source/drain regions have an n-type material.

31. The method of claim 26 further comprising:

removing the resist after forming the first and second halo regions; and

masking the substrate with a second resist before forming the first and second lightly doped regions, the second resist having openings for exposing the first and second halo regions.

32. The method of claim 31 further comprising:

removing the second resist after forming the first and second lightly doped regions; and

masking the substrate with a third resist before forming the first and second source/drain regions, the third resist having openings for exposing the lightly doped regions.

33. The method of claim 26 further comprising:

removing the resist after forming the first and second lightly doped regions; and

masking the substrate with a second resist before forming the first and second source/drain regions, the second resist having openings for exposing the lightly doped regions.

35. The method of claim 34, wherein first and second source/drain regions have a higher doping concentration than the first and second lightly doped regions.

36. The method of claim 34, wherein first and second source/drain regions have a higher doping concentration than the substrate.

37. The method of claim 34, wherein:

the substrate and the first and second halo regions have a first conductivity type; and

the first and second lightly doped regions and the first and second source/drain regions have a second conductivity type different from the first conductivity type.

38. The method of claim 37, wherein:

the substrate and the first and second halo regions have a p-type material; and

the first and second lightly doped regions and the first and second source/drain regions have an n-type material.

40. The method of claim 39, wherein first and second source/drain regions have a higher doping concentration than the first and second lightly doped regions.

41. The method of claim 39, wherein first and second source/drain regions have a higher doping concentration than the substrate.

42. The method of claim 39, wherein:

the substrate and the first and second halo regions have a first conductivity type; and

the first and second lightly doped regions and the first and second source/drain regions have a second conductivity type different from the first conductivity type.

43. The method of claim 42, wherein:

the substrate and the first and second halo regions have a p-type material; and

the first and second lightly doped regions and the first and second source/drain regions have an n-type material.

26. A method of making a semiconductor, the method comprising:

providing a substrate having no gate structure formed above the substrate;

masking the substrate with a resist, the resist having openings for exposing a first exposed area and a second exposed area of the substrate;

forming a first halo region in the first exposed area, and forming a second halo region in the second exposed area;

forming a first lightly doped region within the first halo region;

forming a second lightly doped region within the second halo region;

forming a first source/drain region within the first lightly doped region; and

forming a second source/drain region within the second lightly doped region, wherein the method includes forming no gate above the substrate.

34. A method of making a semiconductor, the method comprising:

providing a substrate having no gate structure formed above the substrate;

masking the substrate with a first resist, the first resist having a first opening and a second opening for exposing a first exposed area and a second exposed area of the substrate; and

implanting dopant into the first exposed area to form a first halo region, and implanting dopant into the second exposed area to form a second halo region, wherein the first and second halo regions are separated by a portion of the substrate having a length equal to a length between the first and the second openings of the first resist;

removing the first resist;

masking the substrate with a second resist, the second resist having a first opening and a second opening for exposing the first and second halo regions;

forming a first lightly doped region within the first halo region, and forming a second lightly within the second halo region;

forming a first source/drain region within the first lightly doped region; and

forming a second source/drain region within the second lightly doped region, wherein the method includes forming no gate above the substrate.

39. A method of making a semiconductor, the method comprising:

providing a substrate having no gate structure formed above the substrate;

masking the substrate with a first resist, the first resist having a first opening and a second opening for exposing a first exposed area and a second exposed area of the substrate;

implanting dopant into the first exposed area to form a first halo region, and implanting dopant into the second exposed area to form a second halo region, wherein the first and second halo regions are separated by a portion of the substrate having a length equal to a length between the first and the second openings of the first resist;

removing the first resist;

masking the substrate with a second resist, the second resist having a first opening and a second opening for exposing the first and second halo regions;

forming a first lightly doped region within the first halo region, and forming a second lightly within the second halo region, wherein the first and second lightly doped regions are separated by distance equal to a length between the first and the second openings of the second resist;

removing the second resist;

masking the substrate with a third resist, the third resist having a first opening and a second opening for exposing the first and second lightly doped regions; and

forming a first source/drain region within the first lightly doped region, and forming a second source/drain region within the second lightly doped region, wherein the method includes forming no gate above the substrate.

44. A method of making a semiconductor, the method comprising:

providing a substrate having no gate structure formed above the substrate;

masking the substrate with a first resist, the first resist having an opening for exposing an exposed area the substrate;

forming a halo region and a lightly doped region in the exposed area;

removing the first resist;

masking the substrate with a second resist, the second resist having a first opening for exposing the halo and the doped regions, and a second opening for exposing a second exposed area of the substrate; and

forming a first source/drain region within the lightly doped region, and forming a second source/drain region in the second exposed area of the substrate, wherein the method includes forming no gate above the substrate.

45. The method of claim 44, wherein first and second source/drain regions have a higher doping concentration than the lightly doped region.

46. The method of claim 44, wherein first and second source/drain regions have a higher doping concentration than the substrate.

47. The method of claim 44, wherein:

the substrate and the halo region have a first conductivity type; and

the lightly doped region and the first and second source/drain regions have a second conductivity type different from the first conductivity type.

48. The method of claim 47, wherein:

the substrate and the halo region have a p-type material; and

the lightly doped region and the first and second source/drain regions have an n-type material.

50. The method of claim 49, wherein masking a second resist include masking the halo and lightly doped regions.

51. The method of claim 49, wherein the first source/drain region is adjacent to the halo region.

52. The method of claim 49, wherein first and second source/drain regions have a higher doping concentration than the lightly doped region.

53. The method of claim 49, wherein first and second source/drain regions have a higher doping concentration than the substrate.

54. The method of claim 49, wherein:

the substrate and the halo region have a first conductivity type; and

the lightly doped region and the first and second source/drain regions have a second conductivity type different from the first conductivity type.

55. The method of claim 54, wherein:

the substrate and the halo region have a p-type material; and

the lightly doped region and the first and second source/drain regions have an n-type material.

49. A method of making a semiconductor, the method comprising:

providing a substrate having no gate structure formed above the substrate;

masking the substrate with a first resist, the first resist having an opening for exposing an exposed area the substrate;

forming a halo region and a lightly doped region in the exposed area;

removing the first resist;

masking the substrate with a second resist, the second resist having a first opening for exposing a second exposed area of the substrate, and a second opening for exposing a third exposed area of the substrate, and

forming a first source/drain region in the second exposed area, and forming a second source/drain region in the third exposed area, wherein the method includes forming no gate above the substrate.