Substrate for semiconductor device, manufacturing method thereof, semiconductor device, and frame main body

• US 20020195695A1
• Filed: 05/23/2002
• Published: 12/26/2002
• Est. Priority Date: 05/30/2001
• Status: Active Grant

• Current Assignee: Sony Corporation (Sony Group Corp.)
• Original Assignee: Sony Corporation (Sony Group Corp.)
• Inventors: Togawa, Miyoshi
• Granted Patent: US 7,129,578 B2
• Time in Patent Office: Days
• US Class Current: 257/678
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 23/13 characterised by the shape
• CPC Class Codes: H01L 23/62 Protection against overvoltage, e.g. fuses, shunts
• CPC Class Codes: H01L 24/45 of an individual wire connector
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/12041 LED
• CPC Class Codes: H01L 2924/181 Encapsulation
• CPC Class Codes: H01L 2924/207 Diameter ranges

Abstract

A lead frame comprises lead frame body having cut-away portions cut away from the side surfaces of the lead frame body, die pad for securing semiconductor chip, bonding electrodes surrounding the die pad, external electrodes for allowing the lead frame to be mounted, wiring for surface treatment extending on the lead frame body with its end being located at a portion of each of the side surfaces of the lead frame body, the portion being opposed the cut-away portions. The bonding electrode and the wiring for surface treatment as well as the external electrode and the wiring for surface treatment are electrically connected, respectively. Even when the lead frame is electrostatically charged by friction with a transfer unit, the semiconductor chip on the lead frame avoids the electrostatic damage.

Claims

1. A substrate for semiconductor device comprising:

insulating substrate body having a cut-away portion cut away from a side surface thereof;

die pad for securing semiconductor chip, said die pad being positioned on said insulating substrate body;

a plurality of bonding electrodes surrounding said die pad;

a plurality of external electrodes for allowing said substrate for semiconductor device to be mounted, each external electrode being electrically connected to said bonding electrode and being positioned under said insulating substrate body;

wiring for surface treatment extending on said insulating substrate body with an end thereof being located at a portion of a side surface of said insulating substrate body, said portion being opposed said cut-away portion, wherein said bonding electrode and said wiring for surface treatment as well as said external electrode and said wiring for surface treatment are electrically connected, respectively.

2. The substrate for semiconductor device as claimed in claim 1, wherein said insulating substrate body includes at least one cut-away portion on each of the opposite sides thereof.

3. The substrate for semiconductor device as claimed in claim 1, wherein said insulating substrate body includes two cut-away portions on each of the opposite sides thereof;

and

wherein said insulating substrate body includes a chucking portion for allowing said insulating substrate body to be chucked, said chucking portion being formed between said two cut-away portions.

4. The substrate for semiconductor device as claimed in claim 1, further comprising wiring for supplying power to said semiconductor chip and for grounding, wherein the wiring for supplying power to said semiconductor chip and for grounding is located at a side surface of said insulating substrate body except for said cut-away portion.

5. The substrate for semiconductor device as claimed in claim 1, further comprising wiring for supplying power to said semiconductor chip and for grounding, wherein the wiring for supplying power to said semiconductor chip and for grounding is located on both sides of said wiring for surface treatment, said wiring for surface treatment being located at said portion of said side surface of said insulating substrate body, and said portion being opposed said cut-away portion, and wherein said wiring for surface treatment is positioned between one wiring for supplying power to said semiconductor chip and for grounding and the other wiring for supplying power to said semiconductor chip and for grounding.

6. The substrate for semiconductor device as claimed in claim 1, wherein said wiring for supplying power to said semiconductor chip and for grounding has width wider than that said wiring for surface treatment has.

7. The substrate for semiconductor device as claimed in claim 1, wherein said surface treatment is an electroplating process.

9. The substrate for semiconductor device as claimed in claim 7, wherein said surface treatment is an electroplating process.

8. A substrate for semiconductor device comprising:

insulating substrate body having an opening therein;

die pad for securing semiconductor chip, said die pad being positioned on said insulating substrate body;

a plurality of bonding electrodes surrounding said die pad;

a plurality of external electrodes for allowing said substrate for semiconductor device to be mounted, each external electrode being electrically connected to said bonding electrode and being positioned under said insulating substrate body;

wiring for surface treatment extending on said insulating substrate body, wherein said opening divides said wiring for surface treatment at midpoint, and wherein said bonding electrode and said wiring for surface treatment as well as said external electrode and said wiring for surface treatment are electrically connected, respectively.

10. A manufacturing method of manufacturing a substrate for semiconductor device, said substrate including insulating substrate body having a cut-away portion cut away from a side surface thereof, die pad for securing semiconductor chip, said die pad being positioned on said insulating substrate body, a plurality of bonding electrodes surrounding said die pad, a plurality of external electrodes for allowing said substrate for semiconductor device to be mounted, each external electrode being electrically connected to said bonding electrode and being positioned under said insulating substrate body, and wiring for surface treatment provided for said bonding electrode and said external electrode, respectively, comprising the steps of:

cutting said wiring for surface treatment after performing said surface treatment on said bonding electrode and said external electrode using said wiring for surface treatment; and

undergoing a mounting operation for mounting said semiconductor chip after said cut processing.

11. The manufacturing method as claimed in claim 10, wherein said surface treatment is an electroplating process.

16. The frame main body as claimed in claim 15, wherein said substrate for semiconductor device further including wiring for supplying power to said semiconductor chip and for grounding.

12. A substrate for semiconductor device comprising:

insulating substrate body;

die pad for securing semiconductor chip, said die pad being positioned on said insulating substrate body;

a plurality of bonding electrodes surrounding said die pad;

a plurality of external electrodes for allowing said substrate for semiconductor device to be mounted, each external electrode being electrically connected to said bonding electrode and being positioned under said insulating substrate body; and

wiring for connection between said bonding electrode and said external electrode, wherein said wiring extends on said insulating substrate body with an end thereof being located at the inside from the side surface of said insulating substrate body.

13. The insulating substrate for semiconductor device as claimed in claim 12, wherein said surface treatment for said bonding electrode and said external electrode is an electroless plating process.

14. A semiconductor device comprising:

a substrate for semiconductor device having insulating substrate body;

a semiconductor chip secured on said substrate for semiconductor device; and

sealing compound for sealing said semiconductor chip, wherein said substrate for semiconductor device provides a bonding electrode on a side on which said semiconductor chip is mounted, wherein said substrate for semiconductor device provides an external electrode for allowing said substrate for semiconductor device to be mounted on the opposite side, and wherein the bonding electrode and the external electrode are provided with wiring for surface treatment, said wiring for surface treatment extending on said insulating substrate body with an end thereof being located at a portion of a side surface of said insulating substrate body, said portion being opposed a cut-away portion cut away from said side surface of said insulating substrate body.

15. A frame main body comprising a plurality of substrates for semiconductor device, each substrate for semiconductor device having a cut-away portion cut and including:

die pad for securing semiconductor chip;

a plurality of bonding electrodes surrounding said die pad;

a plurality of external electrodes for allowing said substrate for semiconductor device to be mounted, each external electrode being electrically connected to said bonding electrode; and

wiring for surface treatment extending on said substrates for semiconductor device with an end thereof being located at a portion of a side surface of said frame main body, said portion being opposed said cut-away portion.

17. A frame main body comprising a plurality of substrates for semiconductor device, each substrate for semiconductor device having an opening therein, and including:

die pad for securing semiconductor chip;

a plurality of bonding electrodes surrounding said die pad;

a plurality of external electrodes for allowing said substrate for semiconductor device to be mounted, each external electrode being electrically connected to said bonding electrode; and

wiring for surface treatment extending on said substrates for semiconductor device, wherein said opening divides said wiring for surface treatment at midpoint.

18. A frame main body comprising a plurality of substrates for semiconductor device, each substrate for semiconductor device including:

die pad for securing semiconductor chip;

a plurality of bonding electrodes surrounding said die pad;

a plurality of external electrodes for allowing said substrate for semiconductor device to be mounted, each external electrode being electrically connected to said bonding electrode; and

wiring for connecting said bonding electrode and said external electrode extending on said substrate for semiconductor device with an end thereof being located at the inside from a side surface of said frame main body.

19. An original plate for providing frame main bodies having openings, comprising a plurality of frame main bodies wherein bus for surface treatment for each frame main body extends between the openings.