Stacked mass storage flash memory package

• US 20020195697A1
• Filed: 06/21/2001
• Published: 12/26/2002
• Est. Priority Date: 06/21/2001
• Status: Active Grant

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: Corisis, David J., Brooks, Jerry M., Mess, Leonard E.
• Granted Patent: US 6,900,528 B2
• Time in Patent Office: Days
• US Class Current: 257/686
• CPC Class Codes: H01L 2224/05553 being rectangular
• CPC Class Codes: H01L 2224/05554 being square
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45124 Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48145 the bodies being stacked
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/4826 Connecting between the body and an opposite side of the item with respect to the body
• CPC Class Codes: H01L 2224/4917 Crossed wires
• CPC Class Codes: H01L 2224/49171 Fan-out arrangements
• CPC Class Codes: H01L 2224/4943 the connecting portions being staggered
• CPC Class Codes: H01L 2224/49433 outside the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/92247 : the second connecting process involving a wire connector
• CPC Class Codes: H01L 2225/06506 : Wire or wire-like electrical connections between devices
• CPC Class Codes: H01L 2225/0651 : Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06555 : Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
• CPC Class Codes: H01L 2225/06562 : at least one device in the stack being rotated or offset
• CPC Class Codes: H01L 2225/06586 : Housing with external bump or bump-like connectors
• CPC Class Codes: H01L 23/3128 : the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/49575 : Assemblies of semiconductor devices on lead frames
• CPC Class Codes: H01L 24/45 : of an individual wire connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/49 : of a plurality of wire connectors
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 29/0657 : characterised by the shape of the body
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01028 : Nickel [Ni]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01039 : Yttrium [Y]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/10158 : at the passive surface
• CPC Class Codes: H01L 2924/10161 : with a rectangular active surface
• CPC Class Codes: H01L 2924/10162 : with a square active surface
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/16195 : Flat cap [not enclosing an internal cavity]
• CPC Class Codes: H01L 2924/1627 : stacked type assemblies, e.g. stacked multi-cavities
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/20752 : larger or equal to 20 microns less than 30 microns

Abstract

A stacked multiple offset chip device is formed of two or more dice of similar dimensions and bond pad arrangement, in which bond pads are located in fields along less than three edges of the active surface of each die. A first die is attached to a substrate and subsequent die or dice are attached in a vertical sequence atop the first die, each in an offset configuration from the next lower die to expose the bond pads thereof for conductive bonding to metallization of the substrate. The multiple chip device permits a plurality of dice to be stacked in a maximum density low profile device. A particularly useful application is the formation of stacked mass storage flash memory package.

Claims

1. A stacked multiple-semiconductor die device, comprising:

a substrate having a surface;

at least one conductive bond area on the surface of the substrate;

a plurality of semiconductor dice having similar dimensions, each semiconductor die having a active surface including at least four edges, and a backside;

a field of conductive bond pads disposed on the active surface of each semiconductor die, the field of conductive pads positioned along less than three edges of the active surface of the semiconductor die, the backside of a first semiconductor die being attached to the substrate surface adjacent the conductive bond areas of said substrate surface and the backside of a second semiconductor die is attached to the active surface of the first semiconductor die in an offset position having the bond pad field of the first semiconductor die being exposed;

conductors connecting bond pads of the first semiconductor die to conductive bond areas of the substrate; and

conductors connecting bond pads of the second semiconductor die to one of conductive bond areas of the substrate and conductive bond pads of the first semiconductor die.

2. The stacked multiple-semiconductor die device of claim 1, wherein said plurality of semiconductor dice comprise a stack of semiconductor dice having one of substantially the same dimensions and different dimensions.

3. The stacked multiple-semiconductor die device of claim 1, comprising at least one additional semiconductor die having a backside attached to at least a portion of the active surface of the next lower semiconductor die in an offset position, the bond pad field of each semiconductor die being exposed for attachment of said conductors thereto.

4. The multiple-semiconductor die stacked device of claim 1, wherein said first semiconductor die is attached to said substrate by a thin adhesive layer and said second die is attached to said first die by a thin adhesive layer.

5. The stacked multiple-semiconductor die device of claim 1, wherein each semiconductor die has a field of bond pads along one edge thereof, and the second semiconductor die being offset from the first semiconductor die in one direction to expose the bond pads of the first semiconductor die for establishing connections from the bond pads to the substrate.

6. The stacked multiple-semiconductor die device of claim 5, further comprising at least one additional semiconductor die fixed in a stack to said second semiconductor die, each additional semiconductor die offset from its underlying semiconductor die, each semiconductor die being offset in the same direction from its underlying semiconductor die.

7. The stacked multiple-semiconductor die device of claim 6, wherein at least one of said semiconductor dice is rotated one of 90, 180, and 270 degrees relative to its underlying semiconductor die.

8. The stacked multiple-semiconductor die device of claim 6, wherein said at least one rotated semiconductor die is an uppermost semiconductor die.

9. The multiple-semiconductor die device of claim 6, wherein said at least one rotated semiconductor die is intermediate the first semiconductor die and the uppermost semiconductor die.

10. The stacked multiple-die device of claim 5, further comprising at least one additional semiconductor die fixed in a stack to said second semiconductor die, each additional semiconductor die offset from its underlying semiconductor die, at least one of the second semiconductor die and the third semiconductor die being rotated 180 degrees relative to said first semiconductor die.

11. The stacked multiple-semiconductor die device of claim 10, wherein each semiconductor die is rotated 180 degrees from its underlying semiconductor die and offset in a reverse direction thereto.

12. The stacked multiple-semiconductor die device of claim 5, further comprising at least one additional semiconductor die fixed in a stack to said second semiconductor die, each additional semiconductor die offset from its underlying semiconductor die, the second semiconductor die and each subsequent semiconductor die being rotated 90 degrees from its semiconductor underlying semiconductor die to position bond pads on at least three sides of the stack.

13. The stacked multiple-semiconductor die device of claim 5, wherein each semiconductor die has a field of bond pads along two adjacent edges thereof, and each of the second semiconductor die and subsequent semiconductor die being offset from its underlying semiconductor die in two directions exposing the bond pads thereof for conductive bonding.

14. The stacked multiple-semiconductor die device of claim 13, wherein each semiconductor die is offset in the same two directions relative to its underlying semiconductor die.

15. The stacked multiple-die device of claim 13, wherein at least one semiconductor die is rotated 180 degrees from its underlying semiconductor die.

16. The stacked multiple-die device of claim 15, wherein at least one rotated semiconductor die includes a topmost semiconductor die.

17. The stacked multiple-semiconductor die device of claim 5, wherein each semiconductor die has a length greater than a width whereby rotation of one semiconductor die relative to an underlying adjacent semiconductor die offsets said first semiconductor die to expose the field of bond pads on said at least one field of bond pads for attaching conductors thereto.

18. The sacked multiple-semiconductor die device of claim 1, comprising:

a lower semiconductor die having a field of bond pads positioned thereon for attachment to conductive wires with loops;

an upper semiconductor die overhanging said field of bond pads by a first height; and

an intervening semiconductor die having an upper surface bonded to said upper semiconductor die with an adhesive layer and a lower surface bonded to said lower semiconductor die with an adhesive layer, said intervening semiconductor die offset from said lower and upper semiconductor dice, the height of overhang between said lower semiconductor die and upper semiconductor die being substantially equal to the thickness of said intervening semiconductor die and two said adhesive layers and said height of overhang exceeding the height of bond wire loops attached to said bond pads of the lower semiconductor die.

19. The high density multiple die stacked device according to claim 18, wherein the intervening semiconductor die includes one of a piece of silicon and an inoperative semiconductor die and an operative semiconductor die.

20. The high density multiple die stacked device according to claim 1, in which said substrate comprises one of a circuit board, circuit card, lead frame and tape automated bonding (TAB) tape.

21. A multiple die stacked device, comprising:

a substrate having conductive areas thereon;

a plurality of semiconductor dice attached in a stack, said stack comprising a first semiconductor die attached to the substrate and subsequent semiconductor dice attached thereto to form said stack, the semiconductor die of the plurality of semiconductor dice in said stack being substantially identical, and the physical orientation of each of said second and subsequent semiconductor die being offset in at least one direction from its underlying semiconductor die and is rotated in one of 0, 90, 180 and 270 degrees relative to said underlying semiconductor die to expose bond pads of the underlying semiconductor die while minimizing the size of the device.

22. A high density stacked multiple-die device, comprising:

a substrate having a surface;

conductive bond areas on the surface of the substrate;

a plurality of semiconductor dice having substantially the same dimensions, each semiconductor die having a rectangular active surface having at least four edges, and a backside;

a field of conductive bond pads disposed on the active surface of each semiconductor die, the field positioned along less than three edges thereof, the backside of a first semiconductor die being attached to the substrate surface adjacent the conductive bond areas of said substrate surface, the backside of a second semiconductor die being attached to the active surface of the first semiconductor die in an offset position having the bond pad field of the first die is exposed;

conductors connecting bond pads of the first semiconductor die to conductive bond areas of the substrate; and

conductors connecting bond pads of the second semiconductor die to one of conductive bond areas of the substrate and conductive bond pads of the first semiconductor die.

23. The high density stacked multiple-die device of claim 22, wherein said plurality of semiconductor dice comprise a stack of semiconductor die, each semiconductor die being one of substantially the same size and of different size.

24. The high density stacked multiple-die device of claim 22, comprising at least one additional semiconductor die having a backside attached to the active surface of the next lower semiconductor die in an offset position, the bond pad field of each semiconductor die exposed for attachment of said conductors thereto.

25. The high density multiple die stacked device of claim 22, wherein said first semiconductor die is attached to said substrate by a thin adhesive layer and said second semiconductor die is attached to said first semiconductor die by a thin adhesive layer.

26. The high density stacked multiple-die device of claim 22, wherein each semiconductor die has a field of bond pads along one edge thereof, and the second semiconductor die is offset from the first semiconductor die in one direction to expose the bond pads of the first semiconductor die for establishing connections from the bond pads to the substrate.

27. The high density stacked multiple-die device of claim 26, further comprising at least one additional semiconductor die fixed in a stack to said second semiconductor die, each additional semiconductor die offset from its underlying semiconductor die, wherein each semiconductor die is offset in the same direction from its underlying semiconductor die.

28. The high density stacked multiple-die device of claim 27, wherein at least one of said semiconductor dice is rotated one of 90, 180, and 270 degrees relative to its underlying semiconductor die.

29. The high density stacked multiple-die device of claim 28, wherein said at least one rotated semiconductor die is an uppermost semiconductor die.

30. The high density stacked multiple-die device of claim 28, wherein said at least one rotated semiconductor die is intermediate the first semiconductor die and the uppermost semiconductor die.

31. The high density stacked multiple-die device of claim 26, further comprising at least one additional semiconductor die fixed in a stack to said second semiconductor die, each additional semiconductor die offset from its underlying die, wherein at least one of the second semiconductor die and the third semiconductor die is rotated 180 degrees relative to said first semiconductor die.

32. The high density stacked multiple-die device of claim 31, wherein each semiconductor die is rotated 180 degrees from its underlying die and offset in a reverse direction thereto.

33. The high density stacked multiple-die device of claim 26, further comprising at least one additional semiconductor die fixed in a stack to said second semiconductor die, each additional semiconductor die offset from its underlying semiconductor die, wherein the second die and each subsequent die is rotated 90 degrees from its underlying semiconductor die to position bond pads on at least three sides of the stack.

34. The high density stacked multiple-die device of claim 26, wherein each semiconductor die has a field of bond pads along two adjacent edges thereof, and each of the second and subsequent semiconductor die is offset from its underlying semiconductor die in two directions exposing the bond pads thereof for conductive bonding.

35. The high density stacked multiple-die device of claim 34, wherein each semiconductor die is offset in the same two directions relative to its underlying semiconductor die.

36. The high density stacked multiple-die device of claim 34, wherein at least one semiconductor die is rotated 180 degrees from its underlying semiconductor die.

37. The high density stacked multiple-die device of claim 36, wherein at least one rotated semiconductor die includes a topmost semiconductor die.

38. The high density stacked multiple-die device of claim 26, wherein each semiconductor die has a length greater than a width whereby rotation of one semiconductor die relative to an underlying adjacent semiconductor die offsets said first semiconductor die to expose the field of bond pads on said at least one field of bond pads for attaching conductors thereto.

39. The high density stacked multiple-die device of claim 22, comprising:

a lower semiconductor die having a field of bond pads positioned thereon for attachment to conductive wires with loops;

an upper semiconductor die overhanging said field of bond pads by a first height; and

an intervening semiconductor die having an upper surface bonded to said upper semiconductor die with an adhesive layer and a lower surface bonded to said lower semiconductor die with an adhesive layer, said intervening semiconductor die offset from said lower semiconductor die and upper semiconductor die, the height of overhang between said lower semiconductor die and upper semiconductor die substantially equals the thickness of said intervening semiconductor die and two said adhesive layers and said height of overhang exceeds the height of bond wire loops attached to said bond pads of the lower semiconductor die.

40. The high density multiple die stacked device according to claim 22, in which said substrate comprises one of a circuit board, circuit card, lead frame and tape automated bonding (TAB) tape.

41. A high density multiple die stacked device, comprising:

a substrate having conductive areas thereon; and

a plurality of semiconductor dice attached in a stack, said stack comprising a first semiconductor die attached to the substrate and subsequent dice attached thereto to form said stack, the semiconductor dice in said stack being similar, and the physical orientation of each of said second semiconductor die and subsequent semiconductor dice being offset in at least one direction from its underlying semiconductor die and rotated in one of 0, 90, 180 and 270 degrees relative to said underlying semiconductor die exposing bond pads of the underlying semiconductor die while minimizing the size of the device.

42. The high density multiple die stacked device of claim 41, wherein one of the semiconductor die includes one of a piece of silicon and an inoperative semiconductor die and an operative semiconductor die.

43. The high density multiple die stacked device of claim 41, wherein one of the semiconductor die includes a piece of silicon.

44. The high density multiple die stacked device of claim 41, wherein the semiconductor die are attached to each other using an adhesive having a thickness of about less than 100 microns.

46. The stacked multiple-semiconductor die device of claim 45, wherein said plurality of semiconductor dice comprise a stack of semiconductor dice having one of substantially different dimensions.

47. The stacked multiple-semiconductor die device of claim 45, comprising at least one additional semiconductor die having a backside attached to at least a portion of the active surface of the next lower semiconductor die in an offset position, the bond pad field of each semiconductor die being exposed for attachment of said conductors thereto.

48. The stacked multiple-semiconductor die device of claim 45, wherein each semiconductor die has a field of bond pads along one edge thereof, and the second semiconductor die being offset from the first semiconductor die in one direction to expose the bond pads of the first semiconductor die for establishing connections from the bond pads to the substrate.

49. The stacked multiple-semiconductor die device of claim 48, further comprising at least one additional semiconductor die fixed in a stack to said second semiconductor die, each additional semiconductor die offset from its underlying semiconductor die, each semiconductor die being offset in the same direction from its underlying semiconductor die.

50. The stacked multiple-semiconductor die device of claim 49, wherein at least one of said semiconductor dice is rotated one of 90, 180, and 270 degrees relative to its underlying semiconductor die.

51. The stacked multiple-die device of claim 49, further comprising at least one additional semiconductor die fixed in a stack to said second semiconductor die, each additional semiconductor die offset from its underlying semiconductor die, at least one of the second semiconductor die and the third semiconductor die being rotated 180 degrees relative to said first semiconductor die.

52. The stacked multiple-semiconductor die device of claim 51, wherein each semiconductor die is rotated 180 degrees from its underlying semiconductor die and offset in a reverse direction thereto.

53. The stacked multiple-semiconductor die device of claim 49, further comprising at least one additional semiconductor die fixed in a stack to said second semiconductor die, each additional semiconductor die offset from its underlying semiconductor die, the second semiconductor die and each subsequent semiconductor die being rotated 90 degrees from its semiconductor underlying semiconductor die to position bond pads on at least three sides of the stack.

54. The stacked multiple-semiconductor die device of claim 49, wherein each semiconductor die has a field of bond pads along two adjacent edges thereof, and each of the second semiconductor die and subsequent semiconductor die being offset from its underlying semiconductor die in two directions exposing the bond pads thereof for conductive bonding.

55. The stacked multiple-semiconductor die device of claim 54, wherein each semiconductor die is offset in the same two directions relative to its underlying semiconductor die.

56. The stacked multiple-die device of claim 54, wherein at least one semiconductor die is rotated 180 degrees from its underlying semiconductor die.

57. The stacked multiple-die device of claim 56, wherein at least one rotated semiconductor die includes a topmost semiconductor die.

58. The stacked multiple-semiconductor die device of claim 49, wherein each semiconductor die has a length greater than a width whereby rotation of one semiconductor die relative to an underlying adjacent semiconductor die offsets said first semiconductor die to expose the field of bond pads on said at least one field of bond pads for attaching conductors thereto.

59. The sacked multiple-semiconductor die device of claim 45, comprising:

a lower semiconductor die having a field of bond pads positioned thereon for attachment to conductive wires with loops;

an upper semiconductor die overhanging said field of bond pads by a first height; and

an intervening semiconductor die having an upper surface bonded to said upper semiconductor die with an adhesive layer and a lower surface bonded to said lower semiconductor die with an adhesive layer, said intervening semiconductor die offset from said lower and upper semiconductor dice, the height of overhang between said lower semiconductor die and upper semiconductor die being substantially equal to the thickness of said intervening semiconductor die and two said adhesive layers and said height of overhang exceeding the height of bond wire loops attached to said bond pads of the lower semiconductor die.

60. The high density multiple die stacked device according to claim 59, wherein the intervening semiconductor die includes one of a piece of silicon and an inoperative semiconductor die and an operative semiconductor die.

61. The high density multiple die stacked device according to claim 45, in which said substrate comprises one of a circuit board, circuit card, lead frame and tape automated bonding (TAB) tape.

45. A multiple-semiconductor die device, comprising:

a substrate having a surface;

at least one conductive bond area on the surface of the substrate;

a plurality of semiconductor dice, each semiconductor die having one of similar dimensions and different dimensions, each semiconductor die having a active surface including at least four edges, and a backside;

a field of conductive bond pads disposed on the active surface of each semiconductor die, the field of conductive pads positioned along less than three edges of the active surface of the semiconductor die, the backside of a first semiconductor die being attached to the substrate surface adjacent the conductive bond areas of said substrate surface and the backside of a second semiconductor die is attached to the active surface of the first semiconductor die in an offset position having the bond pad field of the first semiconductor die being exposed;

conductors connecting bond pads of the first semiconductor die to conductive bond areas of the substrate; and

conductors connecting bond pads of the second semiconductor die to one of conductive bond areas of the substrate and conductive bond pads of the first semiconductor die.

62. A multiple die stacked device, comprising:

a substrate having conductive areas thereon;

a plurality of semiconductor dice attached in a stack, said stack comprising a first semiconductor die attached to the substrate and subsequent semiconductor dice attached thereto to form said stack, the semiconductor die of the plurality of semiconductor dice in said stack being substantially different, and the physical orientation of each of said second and subsequent semiconductor die being offset in at least one direction from its underlying semiconductor die and is rotated in one of 0, 90, 180 and 270 degrees relative to said underlying semiconductor die to expose bond pads of the underlying semiconductor die while minimizing the size of the device.

63. A high density stacked multiple-die device, comprising:

a substrate having a surface;

conductive bond areas on the surface of the substrate;

a plurality of semiconductor dice having substantially different dimensions, each semiconductor die having a rectangular active surface having at least four edges, and a backside;

a field of conductive bond pads disposed on the active surface of each semiconductor die, the field positioned along less than three edges thereof, the backside of a first semiconductor die being attached to the substrate surface adjacent the conductive bond areas of said substrate surface, the backside of a second semiconductor die being attached to the active surface of the first semiconductor die in an offset position having the bond pad field of the first die is exposed;

p1 conductors connecting bond pads of the first semiconductor die to conductive bond areas of the substrate; and

conductors connecting bond pads of the second semiconductor die to one of conductive bond areas of the substrate and conductive bond pads of the first semiconductor die.

64. The high density stacked multiple-die device of claim 63, wherein said plurality of semiconductor dice comprise a stack of semiconductor die, each semiconductor die being one of substantially the same size and of different size.

65. The high density stacked multiple-die device of claim 63, comprising at least one additional semiconductor die having a backside attached to the active surface of the next lower semiconductor die in an offset position, the bond pad field of each semiconductor die exposed for attachment of said conductors thereto.

66. The high density stacked multiple-die device of claim 63, wherein each semiconductor die has a field of bond pads along one edge thereof, and the second semiconductor die is offset from the first semiconductor die in one direction to expose the bond pads of the first semiconductor die for establishing connections from the bond pads to the substrate.

67. The high density stacked multiple-die device of claim 66, further comprising at least one additional semiconductor die fixed in a stack to said second semiconductor die, each additional semiconductor die offset from its underlying semiconductor die, wherein each semiconductor die is offset in the same direction from its underlying semiconductor die.

68. The high density stacked multiple-die device of claim 67, wherein at least one of said semiconductor dice is rotated one of 90, 180, and 270 degrees relative to its underlying semiconductor die.

69. The high density stacked multiple-die device of claim 68, wherein said at least one rotated semiconductor die is an uppermost semiconductor die.

70. The high density stacked multiple-die device of claim 68, wherein said at least one rotated semiconductor die is intermediate the first semiconductor die and the uppermost semiconductor die.

71. The high density stacked multiple-die device of claim 66, further comprising at least one additional semiconductor die fixed in a stack to said second semiconductor die, each additional semiconductor die offset from its underlying die, wherein at least one of the second semiconductor die and the third semiconductor die is rotated 180 degrees relative to said first semiconductor die.

72. The high density stacked multiple-die device of claim 71, wherein each semiconductor die is rotated 180 degrees from its underlying die and offset in a reverse direction thereto.

73. The high density stacked multiple-die device of claim 66, further comprising at least one additional semiconductor die fixed in a stack to said second semiconductor die, each additional semiconductor die offset from its underlying semiconductor die, wherein the second die and each subsequent die is rotated 90 degrees from its underlying semiconductor die to position bond pads on at least three sides of the stack.

74. The high density stacked multiple-die device of claim 66, wherein each semiconductor die has a field of bond pads along two adjacent edges thereof, and each of the second and subsequent semiconductor die is offset from its underlying semiconductor die in two directions exposing the bond pads thereof for conductive bonding.

75. The high density stacked multiple-die device of claim 74, wherein each semiconductor die is offset in the same two directions relative to its underlying semiconductor die.

76. The high density stacked multiple-die device of claim 74, wherein at least one semiconductor die is rotated 180 degrees from its underlying semiconductor die.

77. The high density stacked multiple-die device of claim 76, wherein at least one rotated semiconductor die includes a topmost semiconductor die.

78. The high density stacked multiple-die device of claim 66, wherein each semiconductor die has a length greater than a width whereby rotation of one semiconductor die relative to an underlying adjacent semiconductor die offsets said first semiconductor die to expose the field of bond pads on said at least one field of bond pads for attaching conductors thereto.

79. The high density stacked multiple-die device of claim 63, comprising:

a lower semiconductor die having a field of bond pads positioned thereon for attachment to conductive wires with loops;

an upper semiconductor die overhanging said field of bond pads by a first height; and

an intervening semiconductor die having an upper surface bonded to said upper semiconductor die with an adhesive layer and a lower surface bonded to said lower semiconductor die with an adhesive layer, said intervening semiconductor die offset from said lower semiconductor die and upper semiconductor die, the height of overhang between said lower semiconductor die and upper semiconductor die substantially equals the thickness of said intervening semiconductor die and two said adhesive layers and said height of overhang exceeds the height of bond wire loops attached to said bond pads of the lower semiconductor die.

80. The high density multiple die stacked device according to claim 63, in which said substrate comprises one of a circuit board, circuit card, lead frame and tape automated bonding (TAB) tape.

81. A high density multiple die stacked device, comprising:

a substrate having conductive areas thereon; and

a plurality of semiconductor dice attached in a stack, said stack comprising a first semiconductor die attached to the substrate and subsequent dice attached thereto to form said stack, the semiconductor dice in said stack having at least two different sizes of semiconductor die, and the physical orientation of each of said second semiconductor die and subsequent semiconductor dice being offset in at least one direction from its underlying semiconductor die and rotated in one of 0, 90 , 180 and 270 degrees relative to said underlying semiconductor die exposing bond pads of the underlying semiconductor die while minimizing the size of the device.

82. The high density multiple die stacked device of claim 81, wherein one of the semiconductor die includes one of a piece of silicon and an inoperative semiconductor die and an operative semiconductor die.

83. The high density multiple die stacked device of claim 81, wherein one of the semiconductor die includes a piece of silicon.

84. The high density multiple die stacked device of claim 81, wherein the semiconductor die are attached to each other using an adhesive having a thickness of about less than 100 microns.

85. A high density multiple die stacked device, comprising:

a substrate having conductive areas thereon; and

a plurality of semiconductor dice attached in a stack, said stack comprising a first semiconductor die attached to the substrate and subsequent dice attached thereto to form said stack, the semiconductor dice in said stack having at least two different sizes of semiconductor die, the size of the bottom semiconductor die in the stack being smaller in at least one dimension of length, width, and thickness than a corresponding dimension of at least one other semiconductor die in the stack, and the physical orientation of each of said second semiconductor die and subsequent semiconductor dice being offset in at least one direction from its underlying semiconductor die and rotated in one of 0, 90, 180 and 270 degrees relative to said underlying semiconductor die exposing bond pads of the underlying semiconductor die while minimizing the size of the device.

86. The high density multiple die stacked device of claim 85, wherein one of the semiconductor die includes one of a piece of silicon and an inoperative semiconductor die and an operative semiconductor die.

87. The high density multiple die stacked device of claim 85, wherein one of the semiconductor die includes a piece of silicon.

88. The high density multiple die stacked device of claim 85, wherein the semiconductor die are attached to each other using an adhesive having a thickness of about less than 100 microns.

89. The high density multiple die stacked device of claim 85, wherein at least two dimensions of the bottom semiconductor die of length, width, and thickness are smaller in at least one dimension of length, width, and thickness than a corresponding dimension of at least one other semiconductor die in the stack

90. A high density multiple die stacked device, comprising:

a substrate having conductive areas thereon; and

a plurality of semiconductor dice attached in a stack, said stack comprising a first semiconductor die attached to the substrate and subsequent dice attached thereto to form said stack, the semiconductor dice in said stack having at least two different sizes of semiconductor die, the size of the semiconductor die on the bottom of the stack having at least one dimension of one of length, width, and thickness which is larger than a corresponding dimension of at least another semiconductor die in the stack, and the physical orientation of each of said second semiconductor die and subsequent semiconductor dice being offset in at least one direction from its underlying semiconductor die and rotated in one of 0, 90, 180 and 270 degrees relative to said underlying semiconductor die exposing bond pads of the underlying semiconductor die while minimizing the size of the device.

91. The high density multiple die stacked device of claim 90, wherein one of the semiconductor die includes one of a piece of silicon and an inoperative semiconductor die and an operative semiconductor die.

92. The high density multiple die stacked device of claim 90, wherein one of the semiconductor die includes a piece of silicon.

93. The high density multiple die stacked device of claim 90, wherein the semiconductor die are attached to each other using an adhesive having a thickness of about less than 100 microns.

94. The high density multiple die stacked device of claim 90, wherein at least two dimensions of the bottom semiconductor die of length, width, and thickness are larger in at least one dimension of length, width, and thickness than a corresponding dimension of at least one other semiconductor die in the stack