Plasma treating apparatus, plasma treating method and method of manufacturing semiconductor device

• US 20020197877A1
• Filed: 06/21/2002
• Published: 12/26/2002
• Est. Priority Date: 06/25/2001
• Status: Active Grant

• Current Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Original Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Inventors: Arita, Kiyoshi, Haji, Hiroshi, Iwai, Tetsuhiro, Sakemi, Shoji
• Granted Patent: US 7,074,720 B2
• Time in Patent Office: Days
• US Class Current: 438/710
• CPC Class Codes: H01J 37/3244 Gas supply means
• CPC Class Codes: H01J 37/32532 Electrodes
• CPC Class Codes: H01L 21/304 Mechanical treatment, e.g. grinding, polishing, cutting H01L21/30625 takes precedence
• CPC Class Codes: H01L 21/3065 Plasma etching; Reactive-ion etching
• CPC Class Codes: H01L 21/67092 Apparatus for mechanical treatment or grinding or cutting, see the relevant groups in subclasses B24B or B28D
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 21/6836 Wafer tapes, e.g. grinding or dicing support tapes adhesive tapes in general C09J7/20
• CPC Class Codes: H01L 21/78 with subsequent division of the substrate into plural individual devices cutting to change the surface-physical characteristics or shape of semiconductor bodies H01L21/304
• CPC Class Codes: H01L 2221/68327 used during dicing or grinding
• CPC Class Codes: H01L 2221/6834 used to protect an active side of a device or wafer

Abstract

In a plasma treating apparatus, a ceramic porous substance having a three-dimensional network structure in which a frame portion 18a formed of ceramic containing alumina is provided continuously like a three-dimensional network is used for the material of an electrode member 17 for the plasma treating apparatus to be attached to the front surface of a gas supplying port of an electrode for plasma generation, and a gas for plasma generation is caused to pass through a hole portion 18b formed irregularly in the three-dimensional network structure. Consequently, the distribution of the gas to be supplied is made uniform to prevent an abnormal discharge so that uniform etching having no variation can be carried out.

Claims

1. A plasma treating apparatus comprising:

a treatment chamber;

a first electrode having a holding portion for holding a silicon based substrate in the treatment chamber;

a second electrode provided in a position opposed to the first electrode and having a gas supplying port for supplying a gas for plasma generation to the treatment chamber;

a pressure control portion for reducing a pressure in the treatment chamber;

a gas supplying portion for supplying a mixed gas containing fluorine and helium as the gas for plasma generation to the treatment chamber through the gas supplying port;

a high frequency generating portion for applying a high frequency voltage between the first electrode and the second electrode; and

an electrode member to be attached to a front surface of the gas supplying port,

wherein the electrode member has a three-dimensional network structure and a clearance of the three-dimensional network structure constitutes a plurality of irregular paths for causing the gas for plasma generation to pass therethrough.

2. The plasma treating apparatus according to claim 1, wherein a material forming the three-dimensional network structure contains alumina.

3. The plasma treating apparatus according to claim 1, wherein the work is a silicon based substrate having a damage layer formed thereon by mechanical polishing or grinding and the damage layer is removed by plasma etching.

4. The plasma treating apparatus according to claim 1, wherein the work is a semiconductor wafer having a circuit pattern formed on a surface side and a damage layer provided on a back side of the semiconductor wafer is removed by plasma etching.

5. A plasma treating method in a plasma treating apparatus comprising a treatment chamber, a first electrode having a holding portion for holding a silicon based substrate in the treatment chamber, a second electrode provided in a position opposed to the first electrode and including a gas supplying port for supplying a gas for plasma generation to the treatment chamber and an electrode member having a three-dimensional network structure which is attached to a front surface thereof, a pressure control portion for reducing a pressure in the treatment chamber, a gas supplying portion for supplying a mixed gas containing fluorine and helium as the gas for plasma generation to the treatment chamber through the gas supplying port, and a high frequency generating portion for applying a high frequency voltage between the first electrode and the second electrode, the method comprising the steps of:

applying a high frequency voltage between the first electrode and the second electrode while blowing off the gas for plasma generation from an irregular path constituted by a clearance of the three-dimensional network structure, thereby generating a plasma, and

etching a semiconductor wafer held in the first electrode by the generated plasma.

6. The plasma treating method according to claim 5, wherein the work is a silicon based substrate having a damage layer formed thereon by mechanical polishing or grinding and the damage layer is removed by plasma etching.

7. The plasma treating method according to claim 5, wherein the work is a semiconductor wafer having a circuit pattern formed on a surface side and a damage layer provided on a back side of the semiconductor wafer is removed by plasma etching.

8. A method of manufacturing a semiconductor device having a circuit pattern created on a surface of a semiconductor element, comprising:

a circuit pattern creating step of creating a circuit pattern of a plurality of semiconductor elements on a surface of a semiconductor wafer;

a protective tape sticking step of sticking a protective tape onto the surface of the semiconductor wafer having the circuit pattern created thereon;

a polishing step of mechanically polishing and thinning a back face of the semiconductor wafer;

a washing step of washing the back face of the semiconductor wafer thus polished mechanically and removing a polishing dust generated at the polishing step;

a damage layer removing step of plasma etching the back face of the semiconductor wafer washed at the washing step;

thereby removing a damage layer generated in the mechanical polishing;

a dicing tape sticking step of peeling the protective tape and sticking a dicing tape onto the back face of the semiconductor wafer; and

a dicing step of cutting and dividing the semiconductor wafer having the dicing tape stuck thereto into a unit of the semiconductor element,

wherein the damage layer removing step uses a plasma treating apparatus comprising a first electrode holding the semiconductor wafer with a holding surface which is hermetically stuck to the protective tape and a second electrode which is parallel with the holding surface and has a three-dimensional network structure in a position opposed to the holding surface, and plasma etching is carried out by a plasma generated at a high frequency voltage applied between the first electrode and the second electrode while supplying a gas for plasma generation from an irregular path formed by a clearance of the three-dimensional network structure.

9. The method of manufacturing a semiconductor device according to claim 8, wherein the first electrode is cooled such that the protective tape stuck hermetically to the holding surface is not thermally damaged by heat generated by the plasma.

10. The method of manufacturing a semiconductor device according to claim 8, wherein the gas for plasma generation is a mixed gas containing a fluorine gas and a carrier gas.

11. The method of manufacturing a semiconductor device according to claim 10, wherein the carrier gas is helium.

13. The method of manufacturing a semiconductor device according to claim 12, wherein the first electrode is cooled such that the protective tape stuck hermetically to the holding surface is not thermally damaged by heat generated by the plasma.

14. The method of manufacturing a semiconductor device according to claim 12, wherein the gas for plasma generation is a mixed gas containing a fluorine gas and a carrier gas.

15. The method of manufacturing a semiconductor device according to claim 14, wherein the carrier gas is helium.

12. A method of manufacturing a semiconductor device having a circuit pattern created on a surface of a semiconductor element, comprising:

a circuit pattern creating step of creating a circuit pattern of a plurality of semiconductor elements on a surface of a semiconductor wafer;

a dicing tape sticking step of sticking a dicing tape onto a back face of the semiconductor wafer having the circuit pattern created thereon;

a step of forming a groove for dividing the semiconductor wafer into a unit of the semiconductor element on the surface of the semiconductor wafer stuck to the dicing tape;

a protective tape sticking step of sticking a protective tape to the surface of the semiconductor wafer provided with the groove;

a polishing step of mechanically polishing and thinning the back face of the semiconductor wafer to have such a thickness as to reach the groove, thereby dividing the semiconductor wafer into the unit of the semiconductor element;

a washing step of washing, with a liquid, the back face of the semiconductor wafer thus divided by the mechanical polishing and removing a polishing dust generated at the polishing step; and

a damage layer removing step of plasma etching the back face of the semiconductor wafer divided after the washing step, thereby removing a damage layer generated in the mechanical polishing,

wherein the damage layer removing step uses a plasma treating apparatus comprising a first electrode holding the semiconductor wafer with a holding surface which is hermetically stuck to the protective tape and a second electrode which is parallel with the holding surface and has a three-dimensional network structure in a position opposed to the holding surface, and plasma etching is carried out by a plasma generated at a high frequency voltage applied between the first electrode and the second electrode while supplying a gas for plasma generation from an irregular path formed by a clearance of the three-dimensional network structure.