Method of protecting intellectual property cores on field programmable gate array

• US 20020199110A1
• Filed: 06/13/2002
• Published: 12/26/2002
• Est. Priority Date: 06/13/2001
• Status: Abandoned Application

• Current Assignee: Algotronix Ltd.
• Original Assignee: Algotronix Ltd.
• Inventors: Kean, Thomas A.
• Application Number:
  US10/172,802
• Publication Number:
  US 20020199110A1
• Time in Patent Office: Days
• US Class Current: 713/189
• CPC Class Codes: G06F 21/125 by manipulating the program code, e.g. source code, compiled code, interpreted code, machine code
• CPC Class Codes: G06F 21/76 in application-specific integrated circuits [ASIC] or field-programmable devices, e.g. field-programmable gate arrays [FPGA] or programmable logic devices [PLD]
• CPC Class Codes: G06F 2115/08 Intellectual property [IP] blocks or IP cores
• CPC Class Codes: G06F 30/34 for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
• CPC Class Codes: G06Q 30/06 Buying, selling or leasing transactions

Abstract

Techniques are used to protect intellectual property cores on field programmable gate arrays. An approach is to associate each field programmable gate array, or a limited number of field programmable gate arrays, with a secret key. Each field programmable gate array may only be properly configured or programmed by an appropriate encrypted bitstream (which includes one or more intellectual property cores). This encrypted bitstream has been encoded by or for the secret key associated with a particular FPGA. Other techniques are also presented in this application and include network-based, nonnetwork-based, software-based, layered, and other approaches. The techniques allow an intellectual property core vendor to charge a customer per-use or per-configuration of their intellectual property. This is because an encrypted bitstream is useable only in a limited number, possibly just one, of the integrated circuits.

Claims

1. A method comprising:

manufacturing field programmable gate array integrated circuits, each integrated circuit having an identification code and a secret cryptographic key; and

creating a database of identification codes and secret cryptographic keys, wherein a field programmable gate array integrated circuit with a particular identification code is configurable using a bitstream encrypted using a secret cryptographic key associated with the particular identification code.

2. The method of claim 1 wherein each field programmable gate array integrated circuit has a unique identification code.

3. The method of claim 1 wherein the database is stored on a computer-readable medium.

4. The method of claim 1 wherein the database is stored on at least one of a magnetic disk or an optical disk.

5. The method of claim 1 wherein the identification code and secret cryptographic key are imprinted on each field programmable gate array using a laser.

6. The method of claim 1 wherein the identification code has at least 64 bits.

7. The method of claim 1 wherein the secret cryptographic key has at least 128 bits.

8. A method comprising:

receiving an identification code of a programmable integrated circuit;

obtaining an encryption key associated with the identification code;

encrypting a bitstream file using the encryption key into an encrypted bitstream; and

providing the encrypted bitstream, whereby the encrypted bitstream may be used to configure the programmable integrated circuit with a design as specified in the bitstream file.

9. The method of claim 8 further comprising:

deducting a transaction fee from an account of a customer purchasing the encrypted bitstream.

10. The method of claim 8 further comprising:

crediting an account of a provider of the bitstream file.

11. The method of claim 8 further comprising:

determining the identification code of the programmable integrated circuit by accessing a JTAG interface of the programmable integrated circuit.

12. The method of claim 8 wherein the programmable integrated circuit is a field programmable gate array.

13. The method of claim 8 wherein obtaining an encryption key comprises looking up in a database an encryption key associated with the identification code.

14. The method of claim 8 wherein obtaining an encryption key comprises generating the encryption key using the identification code.

15. The method of claim 8 wherein the bitstream file comprises IP cores of two or more IP core vendors and the method further comprises:

crediting accounts of the two or more IP core vendors.

16. The method of claim 8 wherein obtaining an encryption key comprises loading an encrypted header file into the programmable integrated circuit.

18. The method of claim 17 wherein the network comprises the Internet, wireless data transfer, optical data transfer, telephone line data transfer, or modem data transfer.

19. The method of claim 17 wherein the identification code is obtained through a JTAG interface of the field programmable gate array integrated circuit.

20. The method of claim 17 wherein the identification code is unique to the field programmable gate array integrated circuit.

17. A method comprising:

receiving a request over a network from a customer to purchase an IP core for a field programmable gate array integrated circuit;

charging the customer a price for the IP core;

obtaining an identification code for the field programmable gate array integrated circuit; and

sending over the network an encrypted bitstream comprising the IP core, wherein the encrypted bitstream may be used to configure the field programmable gate array integrated circuit with the identification code.

21. A method comprising:

receiving a request over a network from a customer to purchase a design file for configuring a field programmable gate array integrated circuit, wherein the design file comprises one or more IP cores;

charging the customer a price for the design file;

obtaining an identification code for the field programmable gate array integrated circuit; and

sending over the network an encrypted bitstream for the design file, wherein the encrypted bitstream may be used to configure the field programmable gate array integrated circuit with the identification code.

22. The method of claim 21 further comprising:

crediting accounts of one or more IP core vendors of the one or more IP cores included in the design file.

24. The method of claim 23 wherein the first and second encrypted bitstream files comprise the same IP core designs.

23. A method comprising:

receiving a first encrypted bitstream file, which may not be directly used to configure a field programmable gate array; and

decrypting and reencrypting the first encrypted bitstream into a second encrypted bitstream file, which may be used to directly configure the field programmable gate array.

25. A method comprising:

loading and decrypting a first encrypted header in a field programmable gate array using a first key;

determining a second key stored in the first encrypted header;

loading and decrypting a second encrypted header into the field programmable gate array using the second key;

determining a first user identification code stored in the second encrypted header;

comparing the first user identification code stored in the second encrypted header against a second user identification code stored on the field programmable gate array;

if the first and second user identification codes match, loading and decrypting a third encrypted header in the field programmable gate array using the second key; and

configuring the field programmable gate array with bitstream information stored in the third encrypted header if a first checksum stored in the third encrypted header matches a second checksum stored in the second encrypted header.