System and method for synchronizing data transfer across a clock domain boundary

• US 20020199124A1
• Filed: 06/22/2001
• Published: 12/26/2002
• Est. Priority Date: 06/22/2001
• Status: Abandoned Application

• Current Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Original Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Inventors: Adkisson, Richard W.
• Application Number:
  US09/887,793
• Publication Number:
  US 20020199124A1
• Time in Patent Office: Days
• US Class Current: 713/400
• CPC Class Codes: G06F 1/12 Synchronisation of different clock signals provided by a plurality of clock generators
• CPC Class Codes: G06F 5/06 for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor G06F7/78 takes precedence
• CPC Class Codes: H03L 7/06 using a reference signal applied to a frequency- or phase-locked loop
• CPC Class Codes: H04L 7/0012 by comparing receiver clock with transmitter clock
• CPC Class Codes: H04L 7/0045 Correction by a latch cascade

Abstract

A system and method for synchronizing data transfer operations between two circuit portions across a clock domain boundary. A primary clock signal is operable to clock a first circuit portion and a secondary clock signal, generated from the primary clock signal, is operable to clock a second circuit portion. A SYNC pulse signal is generated based on coincident rising edges of the primary and secondary clock signals. A clock synchronizer controller is operable to generate a plurality of control signals based on the SYNC pulse signal for actuating data transfer circuitry disposed between the first and second circuit portions. A SYNC adjuster portion included in the clock synchronizer controller is operable to re-position the SYNC pulse signal by redefining a new coincident rising edge with respect to the primary and secondary clock signals based on a clock skew relative to each other.

Claims

1. A system for synchronizing a first circuit portion operating in a first clock domain that is clocked with a first clock signal and a second circuit portion operating in a second clock domain that is clocked with a second clock signal, comprising:

means for generating a SYNC pulse signal based on a predetermined temporal relationship between said first and second clock signals; and

a clock synchronizer controller operable to generate a plurality of control signals based on said SYNC pulse signal, said clock synchronizer controller including a SYNC adjuster operable to re-position said SYNC pulse signal based on a skew between said first and second clock signals, wherein at least a portion of said plurality of control signals actuate data transfer synchronizer circuitry disposed between said first and second circuit portions.

2. The system as set forth in claim 1, wherein said SYNC adjustor comprises:

a SYNC correct block operable to receive said SYNC pulse signal via a SYNC distributor, said SYNC correct block for correcting said SYNC pulse signal if said SYNC pulse signal has a particular clock period difference with respect to said first clock signal;

a ratio detector coupled to said SYNC correct block for detecting a frequency ratio relationship between said first and second clock signals;

a state/correct block associated with a phase detector for determining a state indicative of a phase difference between said first and second clock signals, said state/correct block operating responsive to said frequency ratio relationship detected by said ratio detector; and

a skew compensator operating responsive to said state to redefine a new coincident rising edge with respect to said first and second clock signals, whereby said SYNC pulse signal is re-aligned so as to correspond with said new coincident rising edges of said first and second clock signals.

3. The system as set forth in claim 2, further comprising a tapline and selection block operable to drive said plurality of control signals at predetermined times based on said SYNC pulse signal.

4. The system as set forth in claim 3, wherein said SYNC distributor comprises a plurality of registers.

5. The system as set forth in claim 3, wherein said data transfer synchronizer circuitry comprises at least one of a CLK1-TO-CLK2 synchronizer operable to facilitate data transmission from said first circuit portion to said second circuit portion and a CLK2-TO-CLK1 synchronizer operable to facilitate data reception by said first circuit portion from said second circuit portion.

6. The system as set forth in claim 5, wherein said plurality of control signals comprises a CLK1-TO-CLK2_VALID signal provided to said first circuit portion and an NDSYNC signal operable to actuate said CLK1-TO-CLK2 synchronizer.

7. The system as set forth in claim 5, wherein said plurality of control signals comprises a CLK2-TO-CLK1_VALID signal provided to said first circuit portion and an NRSYNC signal operable to actuate said CLK2-TO-CLK1 synchronizer.

8. The system as set forth in claim 5, wherein each of said CLK1-TO-CLK2 and CLK2-TO-CLK1 synchronizers includes a set/reset asynchronous flip-flop.

9. The system as set forth in claim 5, wherein said tapline and selection block comprises a plurality of delay registers.

10. The system as set forth in claim 5, wherein each of said plurality of control signals is staged through at least a flip-flop.

11. A method of synchronizing data transfer operations between two circuit portions across a clock domain boundary, comprising the steps:

generating a secondary clock signal from a primary clock signal, wherein said primary clock signal is operable to clock a first circuit portion and said secondary clock signal is operable to clock a second circuit portion;

generating a SYNC pulse signal based on a predetermined temporal relationship between said primary and secondary clock signals;

compensating for a skew between said primary and secondary clock signals and adjusting said SYNC pulse signal, if necessary; and

generating data transfer control signals at appropriate times relative to said primary and secondary clock signals based on said SYNC pulse signal to control data transfer operations between said first and second circuit portions.

12. The method as set forth in claim 11 wherein said secondary clock signal is generated by a phase-locked loop (PLL) based on said primary clock signal.

13. The method as set forth in claim 11, wherein said SYNC pulse signal is generated when a rising edge in said primary clock signal coincides with a rising edge in said secondary clock signal.

14. The method as set forth in claim 11, wherein said SYNC pulse signal is corrected if said SYNC pulse signal has a select clock period difference with respect to said primary clock signal.

15. The method as set forth in claim 11, wherein said step of compensating for a skew is comprised of the steps:

determining a state indicative of a phase difference between said primary and secondary clock signals; and

redefining a new coincident rising edge with respect to said primary and secondary clock signals based on said state.

16. The method as set forth in claim 15, wherein said new coincident rising edges with respect to said primary and secondary clock signals are redefined by adding at least an extra clock cycle when said state indicates that said primary clock signal lags with respect to said secondary clock signal by a predetermined amount.

17. The method as set forth in claim 15, wherein said new coincident rising edges with respect to said primary and secondary clock signals are redefined by deleting at least an extra clock cycle when said state indicates that said secondary clock signal lags with respect to said primary clock signal by a predetermined amount.

18. The method as set forth in claim 11, wherein said data transfer control signals are staged through a plurality of registers before being provided to data transfer synchronizer circuitry disposed between said first and second circuit portions.

19. The method as set forth in claim 11, wherein said primary clock signal comprises a core clock in a computer system.

20. The method as set forth in claim 19, wherein said secondary clock signal comprises a bus clock in a computer system.