Scan path test method

• US 20020199144A1
• Filed: 05/21/2002
• Published: 12/26/2002
• Est. Priority Date: 05/23/2001
• Status: Abandoned Application

• Current Assignee: NEC Electronics Corporation (Renesas Electronics Corporation)
• Original Assignee: NEC Electronics Corporation (Renesas Electronics Corporation)
• Inventors: Yamauchi, Hisashi
• Application Number:
  US10/153,014
• Publication Number:
  US 20020199144A1
• Time in Patent Office: Days
• US Class Current: 714/726
• CPC Class Codes: G01R 31/318536 Scan chain arrangements, e.g. connections, test bus, analog signals

Abstract

A scan test method may include providing initial test values to a plurality of boundary scan flip-flops (231 to 235) in a shift operation mode. In a next clock cycle, next test values may be provided to the plurality of boundary scan flip-flops (231 to 235) in the shift operation mode. A test result may be read from a device under test (241) into a plurality of boundary scan flip-flops (251 and 252) in a normal operation mode. In this way, a test may be conducted on a device under test (241) with only one operation in a normal operation mode and a test pattern may be set with reduced complexity due to normal operating circuits providing test values based on received inputs.

Claims

1. A scan test method for a scan chain of a plurality of scan flip-flops including a first plurality of boundary scan flip-flops, comprising the steps of:

setting initial test values in the first plurality of boundary scan flip-flops through the scan chain in a shift operation mode so that the initial test values are applied to a circuit under test in a first clock cycle; and

setting next test values in the first plurality of boundary scan flip-flops in the shift operation mode so that the next test values are applied to the circuit under test in a next clock cycle wherein the initial test values and the next test values are set in successive clock cycles and are a test pattern for conducting one test.

2. The scan test method according to claim 1, further including the step of:

reading a test result into a second plurality of boundary scan flip-flops from the circuit under test in a normal operation mode.

3. The scan test method according to claim 2, further including the step of:

shifting data values out of the second plurality of boundary scan flip-flops in the shift operation mode.

4. The scan test method according to claim 1, wherein:

the initial test values do not conflict with the next test values.

5. The scan test method according to claim 1, wherein:

the plurality of scan flip-flops read data from a scan input in synchronism with a first clock edge in the shift operation mode and read data from a data input in synchronism with the first clock edge in a normal operation mode.

6. The scan test method according to claim 5, wherein:

the one test is conducted and a test result is read into a second plurality of boundary flip-flops with only one clock cycle executed in the normal operation mode.

7. The scan test method according to claim 1, wherein:

the scan test method tests a semiconductor memory device.

8. A scan test method for a scan chain including first and second scan flip-flops and first and second boundary scan flip-flops wherein the first scan flip-flop is coupled in the scan chain to provide a first scan flip-flop output to a first boundary scan flip-flop input of the first boundary scan flip-flop and the second scan flip-flop is coupled in the scan chain to provide a second scan flip-flop output to a second boundary scan flip-flop input of the second boundary scan flip-flop, comprising the steps of:

setting initial test values in the first and second boundary scan flip-flops and next test values in the first and second scan flip-flops through the scan chain in a shift operation mode so that the initial test values are applied to a circuit under test in a first clock cycle; and

setting the next test values in the first and second boundary scan flip-flops in the shift operation mode so that the next test values are applied to the circuit under test in a next clock cycle wherein the initial test values and the next test values are set in successive clock cycles and are a test pattern for conducting one test.

9. The scan test method according to claim 8, further including the step of:

reading a test result into a third boundary scan flip-flop from the circuit under test in a normal operation mode.

10. The scan test method according to claim 9, further including the step of:

shifting a data value out of the third boundary scan flip-flop in the shift operation mode.

11. The scan test method according to claim 8, wherein:

In a shift operation, the first boundary scan flip-flop provides data to a second scan flip-flop input of the second scan flip-flop.

12. The scan test method according to claim 8, wherein:

the first boundary scan flip-flop reads data from the first boundary scan flip-flop input in synchronism with a first clock edge in the shift operation mode and reads data from a first boundary scan flip-flop data input in synchronism with the first clock edge in a normal operation mode;

the second boundary scan flip-flop reads data from the second boundary scan flip-flop input in synchronism with the first clock edge in the shift operation mode and reads data from a second boundary scan flip-flop data input in synchronism with the first clock edge in the normal operation mode;

the first scan flip-flop reads data from a first scan flip-flop input in synchronism with the first clock edge in the shift operation mode and reads data from a first scan flip-flop data input in synchronism with the first clock edge in the normal operation mode; and

the second scan flip-flop reads data from a second scan flip-flop input in synchronism with the first clock edge in the shift operation mode and reads data from a second scan flip-flop data input in synchronism with the first clock edge in the normal operation mode.

13. The scan test method according to claim 8, wherein:

the one test is conducted and a test result is read into a third boundary flip-flop with essentially only one clock cycle executed in the normal operation mode.

14. The scan test method according to claim 8, wherein:

the scan test method tests a semiconductor device.

16. The scan test method according to claim 15, wherein:

the next test values depend on at least a portion of the initial test values.

17. The scan test method according to claim 15, wherein:

the next test values are set in the first plurality of boundary scan flip-flops independent of the initial test values.

18. The scan test method according to claim 15, further including the step of:

shifting data values out of the second plurality of scan flip-flops in the shift operation mode.

19. The scan test method according to claim 15, wherein:

the scan test method tests a circuit on an integrated circuit.

20. The scan test method according to claim 15, wherein:

a data input to at least one scan flip-flop receives data from an output from a normal flip-flop.

15. A scan test method for a scan chain of a plurality of scan flip-flops including a first plurality of boundary scan flip-flops and the plurality of scan flip-flops operate in a shift operation mode and a normal operation mode, comprising the steps of:

setting initial test values in the first plurality of boundary scan flip-flops through the scan chain in the shift operation mode so that the initial test values are applied to a circuit under test in a first clock cycle;

setting next test values in the first plurality of boundary scan flip-flops in the shift operation mode so that the next text values are applied to the circuit under test in a next clock cycle wherein the initial test values and the next test values are set in successive clock cycles and are a test pattern for conducting one test; and

reading a test result from the circuit under test into a second plurality of boundary scan flip-flops in a normal operation mode wherein the one test is conducted with essentially only one clock cycle executed in the normal operation mode.