Process chamber used in manufacture of semiconductor device, capable of reducing contamination by particulates

• US 20030000648A1
• Filed: 09/05/2002
• Published: 01/02/2003
• Est. Priority Date: 09/23/1998
• Status: Abandoned Application

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Lee, Jae-Hyun, Chung, Ju-Hyuck, Lee, Jang-Eun, Lee, Young-Koo, Kim, Jin-Sung, Cho, Sung-Bum, Cho, Jung-Hun, Park, Sun-Hoo, Park, Jeong-Hyuck, Kim, Hee-Duk, Nam, Shin-Woo, Choi, Jong-Wook
• Application Number:
  US10/234,135
• Publication Number:
  US 20030000648A1
• Time in Patent Office: Days
• US Class Current: 156/345.51
• CPC Class Codes: C23C 16/4583 the substrate being supported substantially horizontally
• CPC Class Codes: C23C 16/4585 Devices at or outside the perimeter of the substrate support, e.g. clamping rings, shrouds
• CPC Class Codes: C23C 16/54 Apparatus specially adapted for continuous coating
• CPC Class Codes: H01J 37/32431 Constructional details of the reactor
• CPC Class Codes: H01J 37/32623 Mechanical discharge control means
• CPC Class Codes: H01J 37/32642 Focus rings
• CPC Class Codes: H01L 21/32136 using plasmas
• CPC Class Codes: H01L 21/6831 using electrostatic chucks
• CPC Class Codes: H01L 21/68735 characterised by edge profile or support profile
• CPC Class Codes: Y10T 117/10 Apparatus

Abstract

A process chamber used in the manufacture of a semiconductor device for etching a material layer on a semiconductor wafer includes an electrostatic chuck for holding the semiconductor wafer, and an annular edge ring which surrounds the side of the semiconductor wafer on the electrostatic chuck to prevent the semiconductor wafer from departing from its original position. The annular edge ring has a first side which faces the side of the semiconductor wafer and contacts firmly with the side of the semiconductor wafer.

Claims

1. A process chamber used in the manufacture of a semiconductor device for etching a material on a semiconductor wafer using plasma, the process chamber comprising:

an electrostatic chuck for holding the semiconductor wafer; and

an annular edge ring, which surrounds a side of the semiconductor wafer on the electrostatic chuck to prevent the semiconductor wafer from departing from its original position, having a first side which faces the side of the semiconductor wafer,

wherein a distance between the side of the semiconductor wafer and the first side is less than 0.15 mm.

2. The process chamber of claim 1, wherein the first side contacts the side of the semiconductor wafer.

3. The process chamber of claim 1, wherein the edge ring has a first upper surface which overlaps the periphery of a bottom surface of the semiconductor wafer and contacts the bottom surface of the semiconductor wafer.

4. The process chamber of claim 1, wherein the edge ring has a second side facing a side of the electrostatic chuck, the second side of the edge ring having a shape such that the contact area between the second side and a side of the electrostatic chuck is minimal.

5. The process chamber of claim 4, wherein the second side of the edge ring is slanted such that only the edge of the second side contacts the side of the electrostatic chuck.

6. The process chamber of claim 1, wherein the edge ring is fixed such that the edge ring cannot rotate.

7. The process chamber of claim 6, wherein the edge ring is fixed by a fixing pin.

8. The process chamber of claim 6, wherein the edge ring is fixed at two or more points separated from each other by a maximum distance.

9. The process chamber of claim 1, wherein the edge ring comprises quartz, silicon or aluminum nitride.

10. The process chamber of claim 1, further comprising a focus ring formed around the edge ring to make distribution of the plasma uniform.

11. A process chamber used in the manufacture of a semiconductor device for etching a material on a semiconductor wafer using plasma, the process chamber comprising:

an electrostatic chuck for holding the semiconductor wafer; and

an annular focus ring, which surrounds a side of the semiconductor wafer on the electrostatic chuck to prevent the semiconductor wafer from departing from its original position and to make the plasma distribution uniform by drawing the plasma, having a first side which faces the side of the semiconductor wafer and contacts the side of the semiconductor wafer.

12. The process chamber of claim 11, wherein the focus ring has a first upper surface portion which overlaps the periphery of a bottom surface of the semiconductor wafer and contacts the bottom surface of the semiconductor wafer.

13. The process chamber of claim 12, wherein the focus ring has a second upper surface portion which is higher than an upper surface of the semiconductor wafer.

14. The process chamber of claim 11, wherein the focus ring has a second side facing a side of the electrostatic chuck, the second side of the edge ring having a shape such that the contact area between the second side and the side of the electrostatic chuck is minimal.

15. The process chamber of claim 14, wherein the second side of the focus ring is slanted such that only the edge of the second side contacts the side of the electrostatic chuck.

16. The process chamber of claim 11, wherein the focus ring is fixed such that the focus ring cannot rotate.

17. The process chamber of claim 16, wherein the focus ring is fixed by at least two fixing pins fixed at points separated from each other by a maximum distance.

18. The process chamber of claim 11, wherein the focus ring contains a flat second upper surface portion.

19. The process chamber of claim 11, wherein the edge ring comprises quartz, silicon or aluminum nitride.

20. The process chamber of claim 11, wherein a surface temperature of the focus ring is maintained to be above at least 50°

C. across the entire surface of the focus ring during etching.

21. The process chamber of claim 11, wherein a surface temperature of the focus ring is maintained to be above or about 60°

C. across the entire surface of the focus ring during etching.

22. The process chamber of claim 20, wherein a second upper surface portion of the focus ring is flat without protrusions, and wherein the thickness of the focus ring is sufficient to maintain about the same temperature throughout the focus ring.

23. The process chamber of claim 22, wherein a thickness of the focus ring from the flat upper surface to the base thereof is equal to or less than 20 mm.

25. The process chamber of claim 24, wherein the gas supply conduit is formed in a gas supply plate.

26. The process chamber of claim 24, wherein the slant angle of the gas supply conduit in the vertical direction is about 2-5 degrees.

27. The process chamber of claim 25, wherein the gas supply plate is formed of quartz, silicon or aluminum nitride.

29. The process chamber of claim 28, wherein heat transfer lines are formed passing near the slit valve, and the number of the heat transfer lines formed near the slit valve is larger than the number of heat transfer lines formed passing through the sidewall.

30. The process chamber of claim 28, wherein the temperature of an upper part of the sidewall, which is positioned above the wafer transfer path, is the same as or higher than the temperature of a lower part of the sidewall during the etching process.

24. A process chamber used in the manufacture of a semiconductor device for etching a material on a semiconductor wafer using plasma, the process chamber comprising:

an electrostatic chuck for holding the semiconductor wafer;

a gas supply conduit, installed facing an upper surface of the semiconductor wafer, for supplying reaction gases to a space over the semiconductor wafer, wherein the gas supply conduit is slanted at a first angle with respect to the vertical direction such that relatively more reaction gases are provided to a center of the semiconductor wafer than to a periphery of the semiconductor wafer; and

a radio frequency power source for forming plasma in the space over the semiconductor wafer by ionizing the supplied reaction gases.

28. A process chamber used in the manufacture of a semiconductor device for etching a material on a semiconductor wafer using plasma, the process chamber comprising:

an electrostatic chuck for holding the semiconductor wafer; and

a slit valve, attached to a sidewall of the process chamber and separated by a first distance from the electrostatic chuck, having a wafer transfer path through which the semiconductor wafer placed above the electrostatic chuck can be loaded or unloaded in the horizontal direction from or to the outside of the process chamber,

wherein the temperature of the slit valve is maintained at a higher temperature than the sidewall of the process chamber during an etching process.

31. A process chamber used in the manufacture of a semiconductor device for depositing a material on a semiconductor wafer, the process chamber comprising:

an electrostatic chuck for holding the semiconductor wafer;

a heater, installed below the wafer chuck, for supplying heat;

a guide ring for guiding the semiconductor wafer, the guide ring installed at the edge of an upper surface of the wafer chuck and separated from the chuck by about 15-25 mm.

32. The process chamber of claim 31, wherein the inner circumference of the guide ring comprises a first portion, protruding toward the semiconductor wafer and separated from the semiconductor wafer by a first interval, and a second portion, separated from the semiconductor wafer by a second interval which is longer than the first interval, to guide the semiconductor wafer.

33. The process chamber of claim 32, wherein the first interval is 0.5-1.0 mm and the second interval is 2-30 mm.

35. A semiconductor device made by the method of claim 34.

36. The method of claim 34, wherein the wafer contacts the focus ring, which is maintained at a substantially uniform temperature throughout its thickness during the etching step.

37. The method of claim 34, wherein the uniform temperature is at least 60°

C.

39. The method of claim 38, wherein the first angle is about 2 to 5 degrees.

40. A semiconductor device made by the method of claim 38.

34. A method of making a semiconductor device, comprising:

placing a semiconductor wafer on a wafer chuck such that a portion of the wafer contacts one of;

(a) an edge ring which prevents lateral deviation of the wafer, and

(b) a focus ring which makes plasma distribution uniform above the wafer; and

etching a layer over the wafer or a portion of the wafer.

38. A method of making a semiconductor device, comprising:

placing a semiconductor wafer on a wafer chuck;

supplying an etching gas toward the wafer at a first angle with respect to the vertical direction such that relatively more etching gas is provided to the center of the wafer than to the periphery of the wafer;

ionizing the etching gas to form an etching gas plasma; and

etching a layer over the wafer or a portion of the wafer.

41. A method of making a semiconductor device, comprising:

loading a semiconductor wafer on a wafer chuck through a wafer transfer path of a slit valve, which is attached to a sidewall of a process chamber and separated by a first distance from the wafer chuck; and

etching a layer over the wafer or a portion of the wafer while maintaining the temperature of the slit valve at a higher temperature than the sidewall of the process chamber during the etching.

42. A semiconductor device made by the method of claim 41.