Three dimensional programmable device and method for fabricating the same

• US 20030001230A1
• Filed: 08/30/2002
• Published: 01/02/2003
• Est. Priority Date: 06/30/2000
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Lowrey, Tyler A.
• Granted Patent: US 7,247,876 B2
• Time in Patent Office: Days
• US Class Current: 257/529
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 2213/71 Three dimensional array
• CPC Class Codes: G11C 2213/72 Array wherein the access device being a diode
• CPC Class Codes: H01L 29/16 including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
• CPC Class Codes: H01L 29/861 Diodes
• CPC Class Codes: H10B 63/20 comprising selection components having two electrodes, e.g. diodes
• CPC Class Codes: H10B 63/84 arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays
• CPC Class Codes: H10N 70/063 by etching of pre-deposited switching material layers, e.g. lithography
• CPC Class Codes: H10N 70/231 based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
• CPC Class Codes: H10N 70/826 adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
• CPC Class Codes: H10N 70/8413 adapted for resistive heating
• CPC Class Codes: H10N 70/8828 Tellurides, e.g. GeSbTe

Abstract

A three-dimensional memory device having polycrystalline silicon diode isolation elements for phase change memory cells and method for fabricating the same. The memory device includes a plurality of stacked memory cells to form a three-dimensional memory array. The polycrystalline silicon diode element selects the phase change memory cell. The memory device is fabricated by forming a plurality of phase change memory cells and diode isolation elements on a base layer. Additional layers of memory cells and isolation elements are formed over the initial layer.

Claims

1. An apparatus comprising:

in a plurality of planes over a circuit level substrate, individual programmable cells, each cell comprising a volume of programmable material;

at least one contact; and

an electrode coupled to the volume of programmable material and disposed between the volume of programmable material and the at least one contact, the electrode comprising at least two portions having different resistance values.

2. The apparatus of claim 1, where each electrode in a programmable cell is formed in a dielectric layer between the at least one contact and the volume of programmable material, the dielectric layer comprising an aspect ratio (height to width) on the order of 2.5:

1.

3. The apparatus of claim 2, wherein each electrode in the programmable cell is formed in a via formed in the dielectric layer between the at least one contact and the programmable material, and the electrode comprises two distinct portions only one of which is disposed directly adjacent the volume of programmable material.

4. The apparatus of claim 1, wherein an isolation device separates the electrode and the at least one contact in each programmable cell.

5. The apparatus of claim 1, wherein each programmable cell includes a first contact and a second contact, at least one of the first contact and the second contact being shared by programmable cells in adjacent planes.

6. The apparatus of claim 4, where each isolation element is a polysilicon diode.

7. The apparatus of claim 1, wherein the programmable material of each individual programmable cell is a chalcogenide material.

8. The apparatus of claim 1, further comprising:

a base insulator layer to support the plurality of planes over the circuit level substrate.

9. The apparatus of claim 1, further comprises:

an insulation layer formed between a plurality of individual programmable cells in a first plane and a plurality of individual programmable cells in a second different plane.

15. A method of claim 9, further comprising:

forming a dielectric layer between the at least one contact and the programmable material in each programmable cell plane, wherein the electrode is formed in the dielectric material.

10. A memory device comprising:

a plurality of programmable cells in a stacked configuration on a circuit level substrate, each of the plurality of programmable cells comprising a volume of programmable material disposed between a first contact and a second contact, the programmable material coupled to one of the first contact and the second contact by an electrode,

wherein at least one of the first contact and the second contact is shared between adjacent programmable cells.

11. The apparatus of claim 10, wherein each electrode comprises at least two portions having different resistance values.

12. The apparatus of claim 10, wherein each electrode in a programmable cell is formed in a dielectric layer between the at least one contact and the volume of programmable material, the dielectric layer comprising an aspect ratio (height to width) on the order of 2.5:

1.

13. The apparatus of claim 10, the apparatus further comprising:

a first plurality of signal lines, respective ones of the plurality of signal lines coupled to at least one of the plurality of programmable cells.

16. The method of claim 10, wherein the dielectric layer comprises an aspect ratio (height to width) on the order of 2.5:

1.

17. The method of claim 11, wherein the electrode in each programmable cell is formed in a via formed in the dielectric layer between the at least one contact and the programmable material, and the electrode comprises two distinct portions only one of which is disposed directly adjacent the volume of programmable material.

18. The method of claim 14, further comprising:

forming a base insulation layer such that the base insulation layer is used to support the plurality of programmable cells and isolation elements.

20. The apparatus of claim 19, where each electrode in a programmable cell is formed in a dielectric layer between the at least one contact and the volume of programmable material, the dielectric layer comprising an aspect ratio (height to width) on the order of 2.5:

1.

21. The apparatus of claim 20, wherein each electrode in the programmable cell is formed in a via formed in the dielectric layer between the at least one contact and the programmable material, and the electrode comprises two distinct portions only one of which is disposed directly adjacent the volume of programmable material.

22. The apparatus of claim 19, wherein wireless communication software is stored in the memory device.

23. The apparatus of claim 19, wherein the processor is configured to process wireless communication data.

14. A method comprising:

forming an array of contacts over a circuit level substrate, a pair of the array of contacts defining a programmable cell plane there being a plurality of cell planes;

forming between contacts a volume of programmable material coupled to at least one contact by an electrode; and

modifying the resistance value of less than the entire portion of the electrode.

19. An apparatus comprising:

a bus;

a processor coupled to the bus;

a wireless interface coupled to the bus;

a memory device including a plurality of planes over a circuit level substrate, individual programmable cells, each cell comprising a volume of programmable material,

at least contact; and

an electrode couple to the volume of programmable material, and disposed between the volume of programmable material and the at least one contact, the electrode comprising at least two portions having different resistance values.