WAFER LEVEL INTERCONNECTION

• US 20030001251A1
• Filed: 01/10/2001
• Published: 01/02/2003
• Est. Priority Date: 01/10/2001
• Status: Active Grant

• Current Assignee: Raytheon Company (Rtx Corporation)
• Original Assignee: Raytheon Company (Rtx Corporation)
• Inventors: Cheever, James L., Ehmke, John C., Ables, Billy D., Goldsmith, Charles L.
• Granted Patent: US 6,512,300 B2
• Time in Patent Office: Days
• US Class Current: 257/685
• CPC Class Codes: B81B 7/0006 Interconnects
• CPC Class Codes: H01L 2225/06517 Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/0652 Bump or bump-like direct electrical connections from substrate to substrate
• CPC Class Codes: H01L 2225/06572 Auxiliary carrier between devices, the carrier having an electrical connection structure
• CPC Class Codes: H01L 2225/06586 Housing with external bump or bump-like connectors
• CPC Class Codes: H01L 23/04 characterised by the shape of the container or parts, e.g. caps, walls
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

RF MicroElectroMechanical Systems (MEMs) circuitry(15) on a first high resistivity substrate (17)is combined with circuitry (11) onsecond low-resisitivity substrate (13) by overlapping the first high resisitivity substrate (17)and MEMs circuitry (15) with the low resisitivity substrate(13) and circuitry (11) with the MEMs circuitry (15)facing the second circuitry (11). A dielectric lid (19) is placed over the MEMs circuitry (15)and between the first substrate (17)and second substrate (13)with an inert gas in a gap (21)over the MEMs circuitry (15). Interconnecting conductors (25,31,35,37,39,41) extend perpendicular and through the high resistivity substrate (17)and through the dielectric lid (19) to make electrical connection with the low resisitivity substrate (13).

Claims

1. In combination:

a first substrate of high resistivity material having first circuitry thereon;

a second substrate of low resistivity material having second circuitry thereon overlappingly spaced over said first substrate and facing said first circuitry; and

interconnecting conductors extending perpendicular to said substrates between said first circuitry on said first substrate and second circuitry on said second substrate.

2. The combination of claim 1 wherein said low resistivity material is silicon germanium (SiGe) ,silicon or gallium arsenide (GaAS).

3. The combination of claim 2 wherein said high resistivity material is high resistivity silicon.

4. The combination of claim 1 wherein said high resisitivity material is high resisitivity silicon.

5. The combination of claim 1 wherein said circuitry on said high resistivity material includes a MEMS structure.

6. The combination of claim 1 wherein a dielectric lid is spaced between said first circuitry and said second circuitry and separating said first and second substrates.

7. The combination of claim 6 wherein said dielectric lid is a glass, Pyrex or quartz lid.

8. The combination of claim 6 wherein said interconnections extend through said lid.

9. The combination of claim 8 wherein said lid is a dielectric lid presenting a gap over said first circuitry.

10. The combination of claim 9 wherein said gap contains an inert environment.

11. The combination o claim 10 wherein said inert invironment is nitrogen gas.

12. The combination of claim 10 wherein said inert environment is a vacuum.

13. The combination of claim 8 including said interconnecting conductors through said high resistivity material.

15. The method of claim 13 wherein said low resistivity substrate is SiGe, silicon or GaAs.

16. The method of claim 13 wherein said first circuitry includes MEMS circuitry.

17. The method of claim 15 wherein said said gap contains an inert gas.

18. The method of claim 16 wherein said lid is of Pyrex material.

19. The method of claim 16 wherein said lid is of glass material.

20. The method of claim 16 wherein said lid is of quartz material.

21. The method of claim 13 wherein said substrate is of SiGe material.

22. The combination of claim 8 wherein said lid is a dielectric lid presenting a gap over said second circuitry.

23. The combination of claim 8 wherein said lid is a dielectric lid presenting a gap over said first and second circuitry

14. A method of interconnecting a first circuit on a high resistivity substrate to a second circuit on a low resistivity substrate comprising the steps of:

placing a dielectric lid structure over said first circuit on said high resisitivity substrate leaving a gap over said first circuit, overlapping said dielectric lid with said second circuit and said low resisitivity second substrate with said first circuit facing said second circuit and connecting said first circuit to said second circuit using interconnecting conductors extending perpendicular to said substrates and through said dielectric lid.