Flexible tape electronics packaging

• US 20030001287A1
• Filed: 06/27/2001
• Published: 01/02/2003
• Est. Priority Date: 06/27/2001
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Sathe, Ajit V.
• Granted Patent: US 6,800,947 B2
• Time in Patent Office: Days
• US Class Current: 257/780
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16235 the bump connector connecting to a via metallisation of the item
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 23/49811 Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads H01L23/49827 takes precedence
• CPC Class Codes: H01L 23/49822 Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 23/4985 Flexible insulating substrates H01L23/49572 and H01L23/49855 take precedence
• CPC Class Codes: H01L 2924/01087 Francium [Fr]
• CPC Class Codes: H01L 2924/15174 in different layers of the multilayer substrate
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H05K 1/112 directly combined with via connections
• CPC Class Codes: H05K 1/141 One or more single auxiliary printed circuits mounted on a main printed circuit, e.g. modules, adapters H05K1/142 and H05K1/147 take precedence
• CPC Class Codes: H05K 3/0097 Processing two or more printed circuits simultaneously, e.g. made from a common substrate, or temporarily stacked circuit boards H05K3/0052 takes precedence
• CPC Class Codes: H05K 3/4644 by building the multilayer layer by layer, i.e. build-up multilayer circuits making via holes in the insulating layers H05K3/0011; special circuit boards as base or core whereon the multilayer is built H05K3/4602

Abstract

To decrease the weight and the thickness, and to increase the flexibility, of an electronics package, the package includes an integrated circuit (IC) mounted on a flexible tape substrate. In one embodiment, an IC is mounted on a flexible tape substrate using a ball grid array arrangement; however, other arrangements, including lead bonding, can be used. The flexible tape substrate can comprise conductive traces, vias, and patterns of lands on one or more layers. Methods of fabrication, as well as application of the flexible tape package to an electronic assembly, an electronic system, and a data processing system, are also described.

Claims

1. A method comprising:

forming a thin, flexible substrate having a conductor region adapted to mount an integrated circuit;

forming a plurality of traces in the conductor region; and

forming a plurality of lands coupled to the traces.

2. The method recited in claim 1, wherein the substrate is formed of material from the group comprising a polymeric film, polyimide, polyester, polyparabanic acid, epoxy, and fiberglass.

3. The method recited in claim 1, wherein forming the substrate comprises forming a plurality of layers, each comprising a plurality of traces in the conductor region.

4. The method recited in claim 1, wherein forming the substrate comprises forming a plurality of sprocket holes outside the conductor region.

5. The method recited in claim 1, wherein the lands are arranged in a ball grid array, the method further comprising:

forming solder balls on the plurality of lands.

6. A method comprising:

forming a thin, flexible substrate having a conductor region comprising a plurality of traces and a plurality of lands coupled to the plurality of traces; and

coupling pads on an integrated circuit (IC) to corresponding lands on the substrate.

7. The method recited in claim 6, wherein the substrate is formed of material from the group comprising a polymeric film, polyimide, polyester, polyparabanic acid, epoxy, and fiberglass.

8. The method recited in claim 6, wherein forming the substrate comprises forming a plurality of layers, each comprising a plurality of traces in the conductor region.

9. The method recited in claim 6, wherein forming the substrate comprises forming a plurality of sprocket holes outside the conductor region.

10. The method recited in claim 6 and further comprising before coupling:

forming solder balls on the lands.

11. The method recited in claim 6 and further comprising:

mounting the substrate on an additional substrate.

12. The method recited in claim 11, wherein the additional substrate comprises a printed circuit board.

13. The method recited in claim 11, wherein lands are coupled to corresponding terminals on the additional substrate.

14. The method recited in claim 12 and further comprising before mounting:

forming solder balls on the lands.

15. The method recited in claim 12, wherein the lands are coupled to the terminals using a ball grid array.

16. The method recited in claim 12, wherein leads are coupled between corresponding lands and terminals.

18. The electronic package substrate recited in claim 17, wherein the film is formed of material from the group comprising a polymeric film, polyimide, polyester, polyparabanic acid, epoxy, and fiberglass.

19. The electronic package substrate recited in claim 17, wherein the film comprises a plurality of layers, each comprising a plurality of traces in the conductor region.

20. The electronic package substrate recited in claim 17, wherein the lands are arranged in a ball grid array.

17. An electronic package substrate comprising:

a thin, flexible, electrically insulating film having a conductor region adapted to mount an integrated circuit;

a plurality of traces in the conductor region; and

a plurality of lands coupled to the traces.

21. An electronic package comprising:

an electrically insulating film having a thickness in the range of approximately 0.15 to 0.90 millimeters, the film having a conductor region, a plurality of traces in the conductor region, and a plurality of lands coupled to the traces; and

an electronic component having a plurality of pads coupled to the plurality of lands.

22. The electronic package recited in claim 21, wherein the film is formed of material from the group comprising a polymeric film, polyimide, polyester, polyparabanic acid, epoxy, and fiberglass.

23. The electronic package recited in claim 21, wherein the film comprises a plurality of layers, each comprising a plurality of traces in the conductor region, and wherein each layer has a thickness within the range of approximately 0.15 to 0.30 millimeters.

24. The electronic package recited in claim 21, wherein the lands are arranged in a ball grid array.

25. The electronic package recited in claim 21, wherein the electronic component comprises an integrated circuit.

27. The electronic system recited in claim 26, wherein the film is formed of material from the group comprising a polymeric film, polyimide, polyester, polyparabanic acid, epoxy, and fiberglass.

28. The electronic system recited in claim 26, wherein the film comprises a plurality of layers, each comprising a plurality of traces in the conductor region.

29. The electronic system recited in claim 26, wherein the lands are arranged in a ball grid array.

30. The electronic system recited in claim 26, wherein the electronic component comprises an integrated circuit.

26. An electronic system comprising at least one electronic assembly comprising:

a thin, flexible, electrically insulating film having a conductor region, a plurality of traces in the conductor region, and a plurality of lands coupled to the traces; and

an electronic component having a plurality of pads coupled to the plurality of lands.

31. A data processing system comprising:

a bus coupling components in the data processing system;

a display coupled to the bus;

a memory coupled to the bus; and

a processor coupled to the bus and comprising an electronic assembly including,

a thin, flexible electrically insulating film having a conductor region, a plurality of traces in the conductor region, and a plurality of lands coupled to the traces; and

an integrated circuit having a plurality of pads coupled to the plurality of lands.

32. The data processing system recited in claim 31, wherein the film is formed of material from the group comprising a polymeric film, polyimide, polyester, polyparabanic acid, epoxy, and fiberglass.

33. The data processing system recited in claim 31, wherein the film comprises a plurality of layers, each comprising a plurality of traces in the conductor region.

34. The data processing system recited in claim 31, wherein the lands are arranged in a ball grid array.